Today we celebrate that the Memory Team had both papers submitted to DATE accepted as full papers at the conference. The first paper was written by Manil Dev Gomony and is entitled “Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems”. This paper discusses area, power and performance benefits of coupling the arbitration in a TDM NoC with the memory controller arbitration, thereby reducing the number of arbitration points on the path from processor to memory. The second paper entitled “Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization” was first-authored by Karthik Chandrasekar. This paper shows how to exploit excessive process margins in DRAMs by proposing a methodology for how to determine the minimum timings that a memory can safely run at, thereby improving performance.
Three Presentations at ESWEEK
The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!
Accepted Paper at ESTIMedia 2013
To our great delight, Davit Mirzoyan’s paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” has been accepted at ESTIMedia 2013. The paper extends his earlier work and presents a framework to estimate the probability distribution of application throughput (e.g. frames per second in video decoding) in a system with Voltage-Frequency Island (VFI) partitions in the presence of process variation. The novelty of the framework lies in the computation of the probability distribution of throughput, based on a user-specified set of clock-frequency levels per VFI domain considering both within-die and die-to-die variations of cores. A methodology is furthermore provided to perform variation-aware partitioning of the cores of a MPSoC into VFIs for maximized timing yield (percentage of chips that satisfy a given throughput requirement).
Paper About CompSOC Tool-flow at FPGAworld 2013
A paper about the CompSOC tool-flow has been accepted that describes the highly automated effort of specifying and creating instances of the CompSOC platform, map applications to resources considering their real-time requirements, and executing the resulting system on FPGA. Three sub-flows of the tool-flow and their interactions are briefly explained: 1) the hardware tool flow, capable of translating a high-level description of a CompSOC platform instance into a fully synthesized implementation, 2) A system software flow, generating a software stack including a composable micro kernel, resource managers, drivers, and a virtual platform boot loader, and 3) An application flow that automatically generates a virtual platform configuration for applications that use the Cyclo-static Data Flow (CSDF) model of computation. The paper will be presented at FPGAworld and puts particular emphasis on practical aspects related to the first of these sub-flows and on the interaction with tools for our FPGA target.
Accepted Paper at CODES/ISSS 2013
Our paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” has been accepted at CODES/ISSS 2013. The paper is first-authored by Sven Goossens and builds on the work of Jasper Kuijsten, a graduated master student from the Memory Team. In this paper, we present a new architecture of our real-time memory controller that supports predictable and composable run-time reconfiguration on use-case transitions, which allows trade-offs between guaranteed bandwidth, response time and power. It also presents a methodology for offering composable service to memory clients by means of composable memory patterns, an extension to our existing pattern-based approach. Lastly, a reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol are proposed. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA platform.
Paper Accepted at DSD 2013
Sahar Foroutan had a paper entitled “A General Framework for Average-Case Performance Analysis of Shared Resources” accepted at DSD 2013. This paper is a result of her six month collaboration visit in Eindhoven last year. The two main contributions of the paper are: 1) a general model for resource sharing based on queuing theory that can be used with different arbiters and that captures architectural features of the shared resource, such as pipelining and arbitration delay, and 2) three arbiter models for time-division multiplexing, static-priority arbitration, and round-robin, respectively, that assume general distributions (G/G/1) and fits within the framework.
Paper Accepted at RTCSA 2013
Today, we congratulate Hazem Ali for having his first paper accepted at RTCSA. The paper is entitled “Critical-Path-First Based Allocation of Real-Time Streaming Applications on 2D Mesh-Type Multi-Cores” and proposes a mapping strategy for streaming applications, represented as acyclic data-flow graphs with throughput requirements, to multi-core architectures under partitioned EDF scheduling. The key idea is to first map tasks on the critical-paths of the application to minimize their execution time and thereby increasing the chance to satisfy the throughput constraint. The camera-ready version is available here.
Hazem Ali is a PhD student at the CISTER-ISEP Research Unit in Porto, supervised by Luis Miguel Pinho and myself, and this paper is a result of my six month visit there last year and the fruitful collaboration it has resulted in afterwards.
Article about Variation-aware Mapping Accepted by ACM TECS
ACM Transactions on Embedded Computing Systems (TECS) just accepted our article “Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs”. This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper “Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield”, presented at ISQED in 2012. The camera-ready version is available here.
Paper Accepted at SIES 2013
A paper entitled “Identifying the Sources of Unpredictability in COTS-based Multicore Systems” was accepted at SIES 2013. This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.
Update: The paper is now available online here.
Paper Accepted at DAC 2013
For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.
Update: The paper is now available online. Click here to read it.