Tag: memory patterns

Prestigious Test Of Time Award at ESWEEK 2023 for Memory Controller Research

Posted on by bennyakesson

I am happy to announce that we received the Test Of Time Award for CODES+ISSS at ACM/IEEE Embedded Systems Week (ESWEEK) 2023 in Hamburg, Germany. The Test of Time Award is the most prestigious award of ESWEEK and honors the authors of papers of previous editions of the co-located conferences (CASES 2008, CODES+ISSS 2007, and EMSOFT 2007) that had the highest impact. We received this award for my first paper as a PhD student “Predator: a predictable SDRAM memory controller“, which written with co-authors Kees Goossens and Markus Ringhofer and published in CODES+ISSS 2007.

The paper addressed the problem of providing guarantees on bandwidth and latency to ports on an SDRAM memory controller, a key component of a system-on-chip. Previously, this was only done for statically scheduled memory controllers that assumed the workload of memory requests was known a priori. While this limitation was acceptable for simple systems, increasing integration of functionality in consumer electronics products like set-top boxes challenged this assumption, requiring more dynamic solutions. To this end, the paper presented concepts, hardware architecture, and performance analysis for a more dynamic SDRAM memory controller for real-time systems.

This work formed the base for my memory research, which evolved into a research line that would continue for over a decade and in which six PhD students eventually graduated. In total, this research resulted in a body of work of 30+ papers and two books, which together have been cited more than 2000 times. It also resulted in the open-source tool DRAMPower, which is used to estimate energy consumption of memories. This tool has been integrated in the popular Gem5 simulator and is widely used by the computer architecture community.

The paper was impactful because it was one of the first papers about memory controllers for real-time systems. More papers would follow from Barcelona Supercomputing Center, UC Berkley, and University of Waterloo. Step by step, the proposed memory controllers would become more dynamic and the analysis more sophisticated. This continued until the middle of the previous decade, at which the field moved more from proposing and analyzing new memory controller architectures for systems-on-chips to configuring and analyzing commercial-of-the-shelf memory controllers. This is still an active field of research in the real-time systems community today.

“Receiving this award is an unexpected honor, and I extend my heartfelt thanks to my co-authors and everyone that contributed to subsequent advancements in this field, in particular my former PhD students Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Yonghui Li, and Anna Minaeva. Together, we created, developed, and matured the research field of memory controllers for real-time systems.”

New Book Available for Pre-order

Posted on by bennyakesson

Our new book “Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs” is now available for pre-order at Springer. The book is based on the excellent PhD thesis of Sven Goossens and discusses the design and FPGA implementation of a real-time memory controller for mixed-criticality systems. The controller can provide complete temporal isolation to its clients as well as hard bounds on the worst-case response time of transactions and the bandwidth offered by the memory. In addition, it provides competitive average-case performance for soft real-time and best-effort applications using a conservative open-page policy. The design is highly configurable and the book carefully quantifies the trade-offs between bandwidth, response time, and power that this enables. To facilitate the discussion about power, the book also presents the power model that came out of the PhD dissertation of Karthik Chandrasekar and gives an up-to-date description of the open-source DRAMPower tool that implements it.

Update: The contents of the book are now available on SpringerLink

Sven Goossens Successfully Defended Dissertation

Posted on by bennyakesson

After successfully defending his dissertation “A Reconfigurable Mixed-Time-Criticality SDRAM Controller“, Sven Goossens earned himself a PhD degree and the right to call himself a doctor. The work proposes a pattern-based SDRAM controller targeting mixed-time-criticality systems, i.e. systems where some memory clients need firm worst-case guarantees on bandwidth and latency, while other clients only care about average-case performance. A new memory controller architecture is designed to address this mix of requirements and it is implemented both as a cycle-accurate SystemC simulation model and as synthesizable RTL code for generating FPGA instances. A unique feature of this memory controller is its conservative open-page policy that leaves rows open in the memory banks as long as possible to exploit locality and boost average-case performance, but closes them just in time to avoid reducing the worst-case performance.

The work also parameterizes the concept of memory patterns by allowing the number of banks and the number of bursts per bank to be chosen when the patterns are generated. This allows patterns with different degrees of bank-level parallelism to be created for six different generations of DRAM for any request size, enabling the user to make a trade-off between worst-case bandwidth, worst-case response time, and power consumption. To generate efficient memory patterns, the work proposes an integer linear programming formulation that provides optimal patterns, as well as a near-optimal heuristic that runs in a fraction of the time. In addition to generating predictable memory patterns that provide bounded bandwidth and execution times, composable read and write patterns can be generated with negligible performance loss. These patterns have equal length and can be used to provide complete temporal isolation between memory clients when combined with a non-work-conserving Time-Division Multiplexing (TDM) arbiter in the front-end. The memory patterns are generated offline at design time, but are programmed at run-time when the memory controller is initialized. Lastly, the proposed controller supports run-time reconfiguration of its TDM arbiter, allowing it to be safely reprogrammed when applications dynamically start and stop at run-time without sacrificing the worst-case guarantees of applications that keep running.

I would like to thank Sven for the five years of hard work. It has been a pleasure to work with such a versatile and independent young researcher who seems to be succesful at whatever he attempts, be it design, analysis, writing papers, or hardware/software implementation in more or lesss any language. He has also been an excellent member of the Memory Team and the larger CompSoC Team, never passing on an opportunity to use his skills to support other members of the team. At the end of January, Sven starts his new career with Intrinsic-ID in Eindhoven. We wish him the best of luck with his new job and hope to stay in touch.

Article Accepted in IEEE Transactions on Computer

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The spree of accepted journal articles continues as Sven Goossens’ article entitled “Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling” was accepted for publication in IEEE Transactions on Computers. The article contains a detailed discussion about the trade-offs between bandwidth, execution time, and power when DRAM requests are scheduled by a real-time memory controller under a close-page policy. The results cover a wide range of memories ranging from DDR2/3/4 to LPDDR1/2/3 for different request sizes and amounts of bank parallelism. Other key contributions of the article are: 1) publicly available heuristic and optimal algorithms for generation of memory patters that covers all aforementioned memories, 2) a simple abstraction that quickly captures the differences between the different DRAM generations allowing algorithms and analyses to be easily adapted to cover all of them, and 3) a pairwise bank-group interleaving scheme for DDR4 that exploits bank grouping for improved performance.

Accepted Paper at CODES/ISSS 2013

Posted on by bennyakesson

Our paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” has been accepted at CODES/ISSS 2013. The paper is first-authored by Sven Goossens and builds on the work of Jasper Kuijsten, a graduated master student from the Memory Team. In this paper, we present a new architecture of our real-time memory controller that supports predictable and composable run-time reconfiguration on use-case transitions, which allows trade-offs between guaranteed bandwidth, response time and power. It also presents a methodology for offering composable service to memory clients by means of composable memory patterns, an extension to our existing pattern-based approach. Lastly, a reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol are proposed. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA platform.

Jasper Kuijsten Graduates from the Memory Team

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Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.