Anna Minaeva Successfully Defends Dissertation

Today, Anna Minaeva successfully defended her PhD dissertation entitled “Scalable Scheduling Algorithms for Embedded Systems with Real-Time Requirements” and earned the right to call herself a doctor. The reviewers were pleased with the dissertation and she confidently answered their questions.

The dissertation considers applications with real-time requirements sharing resources, such as memories, cores, and networks, in distributed systems. Scheduling this type of application subject to resource and precedence constraints, among others, while maximizing system performance is a challenging problem. Existing approaches either propose exact solutions that cannot solve industrial-sized instances or propose heuristic algorithms without validating its efficiency with optimal solutions.

The dissertation addresses this problem through a three-stage approach, corresponding to three problems with gradually increasing complexity and accuracy of the model. The four main contributions of are: 1) Comparison of three formalisms to solve the problems optimally, Integer Linear Programming (ILP), Satisfiability Modulo Theory, and Constraint Programming, along with computation time improvements. To increase the scalability of the ILP approach, an optimal approach that wraps the ILP in a branch-and-price framework is presented. 2) For each problem, a scalable and efficient heuristic algorithm is presented that decomposes the problem to decrease its computation time. 3) The efficiency of the optimal and heuristic strategies are quantitatively and qualitatively compared. 4) The practical applicability of the proposed heuristic algorithms and optimal approaches is demonstrated on case studies of real systems in both the automotive and consumer electronics domains.

I wish Anna the best of luck in her future career and hope I will have the opportunity to work with her again.

Hazem Ali Defends Dissertation

Today, Hazem Ali successfully defended his PhD dissertation entitled "Integrating Dataflow and Non-Dataflow Real-time Application Models on Multi-core Platforms" and became a doctor. The main contribution of the thesis is a design flow that integrates applications specified using two different application models, data-flow graphs and periodic real-time task sets, on a shared NoC-based multi-core platform. The committee recognized that the work was building bridges between two different communities in the world of real-time systems and that it was nice that the publications from the PhD work have been nicely integrated into a single design flow.

For those of you that are interested in a short summary of this work, please refer to his publication "Combining Dataflow Applications and Real-time Task Sets on Multi-core Platforms" accepted at the 2017 Workshop on Software and Compilers for Embedded Systems (SCOPES). Lastly, we wish Hazem the best of luck in his future career.

Yonghui Li Defends Dissertation

Today, we celebrate that Yonghui Li successfully defended his PhD dissertation “Design and Formal Analysis of Real-Time Memory Controllers” and became Dr. Li. The thesis defines a dynamically scheduled real-time memory controller architecture, which is implemented as a SystemC simulation model. It then continues by analyzing the worst-case response time and minimum guaranteed bandwidth using three different formal frameworks. The first framework is a mathematical formulation of both the actual and worst-case timing behavior as a set of equations and proofs of their correctness. These equations are also implemented in an open-source tool. The drawback of this kind of mathematical formulation is that it takes a long time to derive and prove correct. The second analysis approach addresses this by shifting the effort of the user from performance analysis to modeling the memory controller as a mode-controlled data-flow graph, which can be analyzed with existing tools. This approach is faster, but only bounds the minimum guaranteed bandwidth and not the worst-case response time. This limitation is overcome by the final approach, which is to model the memory controller using timed automata and bound its worst-case performance using a model checker. So, in summary, one controller architecture and three approaches to analyse its worst-case performance. This work hence gives unique insight into the strengths and weaknesses of different modeling and analysis approaches in terms of accuracy, expressiveness, memory consumption, and computation time.

The defense itself was well-prepared and confident and the committee seemed to really like the work. I am also really pleased with how it came out and I would like to thank Yonghui for the years of hard work that went into creating it. It was a pleasure to work with you during these years and I wish you all the best in your future career.

Sven Goossens Successfully Defended Dissertation

After successfully defending his dissertation “A Reconfigurable Mixed-Time-Criticality SDRAM Controller“, Sven Goossens earned himself a PhD degree and the right to call himself a doctor. The work proposes a pattern-based SDRAM controller targeting mixed-time-criticality systems, i.e. systems where some memory clients need firm worst-case guarantees on bandwidth and latency, while other clients only care about average-case performance. A new memory controller architecture is designed to address this mix of requirements and it is implemented both as a cycle-accurate SystemC simulation model and as synthesizable RTL code for generating FPGA instances. A unique feature of this memory controller is its conservative open-page policy that leaves rows open in the memory banks as long as possible to exploit locality and boost average-case performance, but closes them just in time to avoid reducing the worst-case performance.

The work also parameterizes the concept of memory patterns by allowing the number of banks and the number of bursts per bank to be chosen when the patterns are generated. This allows patterns with different degrees of bank-level parallelism to be created for six different generations of DRAM for any request size, enabling the user to make a trade-off between worst-case bandwidth, worst-case response time, and power consumption. To generate efficient memory patterns, the work proposes an integer linear programming formulation that provides optimal patterns, as well as a near-optimal heuristic that runs in a fraction of the time. In addition to generating predictable memory patterns that provide bounded bandwidth and execution times, composable read and write patterns can be generated with negligible performance loss. These patterns have equal length and can be used to provide complete temporal isolation between memory clients when combined with a non-work-conserving Time-Division Multiplexing (TDM) arbiter in the front-end. The memory patterns are generated offline at design time, but are programmed at run-time when the memory controller is initialized. Lastly, the proposed controller supports run-time reconfiguration of its TDM arbiter, allowing it to be safely reprogrammed when applications dynamically start and stop at run-time without sacrificing the worst-case guarantees of applications that keep running.

I would like to thank Sven for the five years of hard work. It has been a pleasure to work with such a versatile and independent young researcher who seems to be succesful at whatever he attempts, be it design, analysis, writing papers, or hardware/software implementation in more or lesss any language. He has also been an excellent member of the Memory Team and the larger CompSoC Team, never passing on an opportunity to use his skills to support other members of the team. At the end of January, Sven starts his new career with Intrinsic-ID in Eindhoven. We wish him the best of luck with his new job and hope to stay in touch.

Hazem Ali in HiPEAC Newsletter

Last year, my PhD student Hazem Ali got a HiPEAC collaboration grant sponsoring a three month visit in the Electronic Systems group at Eindhoven University of Technology, hosted by Dr. Sander Stuijk. The topic of the joint research is related to the borderland between data-flow and traditional real-time analysis. On page 15 in the latest issue of the HiPEAC Newsletter, you can read more about his stay.

Manil Dev Gomony Successfully Defends PhD Thesis!

Today, Manil Dev Gomony has successfully defended his PhD thesis entitled “Scalable and Bandwidth-Efficient Memory Subsystem Design for Real-Time Systems“. The thesis proposes an architecture for a real-time memory subsystem that scales well in terms of area and maximum synthesizable frequency with an increasing number of memory clients. This subsystem architecture comprises a memory interconnect called Globally Arbitrated Memory Tree (GAMT) a Multi-Channel Memory Controller (MCMC), as well as a technique to couple those components and have a single point of arbitration for both resources. The thesis also proposes a design flow for automatically choosing the memory device, mapping clients to memory channel, and configure arbiters to satisfy client requirements.

Among Manil’s achievements, we specifically highlight two achievements with respect to publishing. First of all, he had a paper accepted at the DATE conference every year during his PhD. Secondly, none of his publications were ever rejected anywhere. This shows that Manil managed to publish in competitive forums in his field and that his work was well-received. Currently, Manil works as a Researcher at Bell Laboratories of Alcatel-Lucent in Belgium. We wish him the best of luck in his future career!

First PhD Student Graduates From the Memory Team

Today, Karthik Chandrasekar was promoted to doctor as he confidently defended his PhD thesis “High-Level Power Estimation and Optimization of DRAMs”. The thesis proposes a high-level power estimation tool called DRAMPowerthat estimates the power and energy consumption of different generations of DRAMs based on a memory command trace and current values from the memory datasheet. Since current numbers in datasheets are often pessimistic for a majority of the manufactured memory devices, a methodology is also proposed to characterize DRAM modules post-manufacturing to achieve more accurate power and performance estimates for the characterized devices. Lastly, the thesis discusses power optimization in the context of real-time memory controllers and proposes two power-down strategies to reduce the power consumption of memories in real-time systems without sacrificing worst-case performance.

The defense went very well and the committee was particularly pleased with how the DRAMPower tool was verified using measurements on real hardware and how it has attracted interest from industry. Karthik is the first PhD student to graduate from the Memory Team and the rest of the team wishes him all the best for his future career at Nvidia.

Davit Mirzoyan Successfully Defends PhD Thesis!

On this day, Davit Mirzoyan confidently defended his PhD thesis, earning the right to call himself a doctor. The thesis is entitled Better than Worst-Case Design for Streaming Applications under Process Variation and discusses how process variation during chip manufacturing can be exploited during application mapping and voltage-frequency island partitioning to increase the number of chips that satisfy the real-time requirements of the application. The work is very interesting, as it captures how variation in transistor parameters affect application performance, thus tying together the lowest and the highest levels of system design.

An interesting fact is that due to circumstances beyond Davits control, he had to write his thesis and send it off to the committee in only two months, something most people would not be able to do, yet he delivered a nice piece of work that was referred to as a ‘very smooth read’ by the committee. As Davits co-promotor, I am very proud of his achievement and I have very much enjoyed working with him during the past four years. I wish him the best of luck in his future career.

Karthik Chandrasekar Receives HiPEAC Collaboration Grant

Today, we celebrate that Karthik Chandrasekar has received a 3 month HiPEAC collaboration grant to visit the group of Prof. Norbert Wehn at Kaiserslautern Institute of Technology. The application process was competitive with approximately 30% of 67 proposals being funded. The grant serves to extend the existing collaboration between our two groups and will be used to conduct research on the hot topic of “Mobile and 3D-Stacked Wide I/O DRAM Power Modeling and Optimization”.