Back in July, I announced that our project proposal “Zero-Waste Computing: Energy Labels for Digital Services” was granted for the Science and Design PhD program at the University of Amsterdam. Now, the Parallel Computing Systems (PCS) group is looking for a suitable PhD candidate for this project. Among other things, this involves modelling and monitoring to determine how energy is consumed in digital services whose computations are distributed over device, edge, and cloud.
Find a more detailed description of the vacancy, as well as instructions for how to apply here. The application period ends on October 18.
Today was the official project kick-off for the research project “Design Space Exploration 2.0: Towards Optimal Design of Complex, Distributed Cyber Physical Systems”. This project is a part of the Partnership Program Mastering Complexity (MasCot), funded by NWO Domain Applied and Engineering Sciences (AES) together with ESI (TNO). The University of Amsterdam and Leiden University are the academic partners, spearheaded by Andy Pimentel and Todor Stefanov. The carrying industrial partner is ASML, but with Philips, Siemens and ESI as parts of the user committee.
The main goal of the project is to extend existing methods for design-space exploration, often developed for on-chip systems, to cover complex distributed cyber-physical systems (dCPS), such as the lithography machines made by ASML. Designers of such systems need quick answers to so-called “what-if” questions with respect to possible design decisions/choices and their consequences on non-functional properties, such as system performance and cost. This calls for efficient and scalable system level design space exploration (DSE) methods that integrate appropriate application workload and system architectures models, simulation and optimization techniques, as well as supporting tools to facilitate the exploration of a wide range of design decisions. However, such DSE technology for complex dCPS does currently not exist. This projects hence tries to answer the question of how perform efficient and effective DSE for complex, distributed cyber-physical systems.
In today’s kick-off meeting, all stakeholders in the project had an opportunity to introduce themselves and refamiliarize themselves with the project and its goals. The two PhD students who will be working on the project, Marius and Faezeh, from UvA and Leiden, respectively, also gave a brief overview of the work they had done in the first three months of the project, which included a literature review and generation of high-level simulation models for different parameter settings.
I am directly involved in this project through my part-time appointment at UvA. As Marius’ second promotor, I will help him on his journey towards a PhD. I also have an interest in this project as an ESI Research Fellow and part of the MasCot Core Team. In this capacity, I am happy to help linking this project to ESI’s applied research projects, in particular at ASML, to exploit possible synergies, and to stimulate exchanges with other projects in the MasCot program.
Today, we celebrate that Yonghui Li successfully defended his PhD dissertation “Design and Formal Analysis of Real-Time Memory Controllers” and became Dr. Li. The thesis defines a dynamically scheduled real-time memory controller architecture, which is implemented as a SystemC simulation model. It then continues by analyzing the worst-case response time and minimum guaranteed bandwidth using three different formal frameworks. The first framework is a mathematical formulation of both the actual and worst-case timing behavior as a set of equations and proofs of their correctness. These equations are also implemented in an open-source tool. The drawback of this kind of mathematical formulation is that it takes a long time to derive and prove correct. The second analysis approach addresses this by shifting the effort of the user from performance analysis to modeling the memory controller as a mode-controlled data-flow graph, which can be analyzed with existing tools. This approach is faster, but only bounds the minimum guaranteed bandwidth and not the worst-case response time. This limitation is overcome by the final approach, which is to model the memory controller using timed automata and bound its worst-case performance using a model checker. So, in summary, one controller architecture and three approaches to analyse its worst-case performance. This work hence gives unique insight into the strengths and weaknesses of different modeling and analysis approaches in terms of accuracy, expressiveness, memory consumption, and computation time.
The defense itself was well-prepared and confident and the committee seemed to really like the work. I am also really pleased with how it came out and I would like to thank Yonghui for the years of hard work that went into creating it. It was a pleasure to work with you during these years and I wish you all the best in your future career.
After successfully defending his dissertation “A Reconfigurable Mixed-Time-Criticality SDRAM Controller“, Sven Goossens earned himself a PhD degree and the right to call himself a doctor. The work proposes a pattern-based SDRAM controller targeting mixed-time-criticality systems, i.e. systems where some memory clients need firm worst-case guarantees on bandwidth and latency, while other clients only care about average-case performance. A new memory controller architecture is designed to address this mix of requirements and it is implemented both as a cycle-accurate SystemC simulation model and as synthesizable RTL code for generating FPGA instances. A unique feature of this memory controller is its conservative open-page policy that leaves rows open in the memory banks as long as possible to exploit locality and boost average-case performance, but closes them just in time to avoid reducing the worst-case performance.
The work also parameterizes the concept of memory patterns by allowing the number of banks and the number of bursts per bank to be chosen when the patterns are generated. This allows patterns with different degrees of bank-level parallelism to be created for six different generations of DRAM for any request size, enabling the user to make a trade-off between worst-case bandwidth, worst-case response time, and power consumption. To generate efficient memory patterns, the work proposes an integer linear programming formulation that provides optimal patterns, as well as a near-optimal heuristic that runs in a fraction of the time. In addition to generating predictable memory patterns that provide bounded bandwidth and execution times, composable read and write patterns can be generated with negligible performance loss. These patterns have equal length and can be used to provide complete temporal isolation between memory clients when combined with a non-work-conserving Time-Division Multiplexing (TDM) arbiter in the front-end. The memory patterns are generated offline at design time, but are programmed at run-time when the memory controller is initialized. Lastly, the proposed controller supports run-time reconfiguration of its TDM arbiter, allowing it to be safely reprogrammed when applications dynamically start and stop at run-time without sacrificing the worst-case guarantees of applications that keep running.
I would like to thank Sven for the five years of hard work. It has been a pleasure to work with such a versatile and independent young researcher who seems to be succesful at whatever he attempts, be it design, analysis, writing papers, or hardware/software implementation in more or lesss any language. He has also been an excellent member of the Memory Team and the larger CompSoC Team, never passing on an opportunity to use his skills to support other members of the team. At the end of January, Sven starts his new career with Intrinsic-ID in Eindhoven. We wish him the best of luck with his new job and hope to stay in touch.
Last year, my PhD student Hazem Ali got a HiPEAC collaboration grant sponsoring a three month visit in the Electronic Systems group at Eindhoven University of Technology, hosted by Dr. Sander Stuijk. The topic of the joint research is related to the borderland between data-flow and traditional real-time analysis. On page 15 in the latest issue of the HiPEAC Newsletter, you can read more about his stay.
Today, Manil Dev Gomony has successfully defended his PhD thesis entitled “Scalable and Bandwidth-Efficient Memory Subsystem Design for Real-Time Systems“. The thesis proposes an architecture for a real-time memory subsystem that scales well in terms of area and maximum synthesizable frequency with an increasing number of memory clients. This subsystem architecture comprises a memory interconnect called Globally Arbitrated Memory Tree (GAMT) a Multi-Channel Memory Controller (MCMC), as well as a technique to couple those components and have a single point of arbitration for both resources. The thesis also proposes a design flow for automatically choosing the memory device, mapping clients to memory channel, and configure arbiters to satisfy client requirements.
Among Manil’s achievements, we specifically highlight two achievements with respect to publishing. First of all, he had a paper accepted at the DATE conference every year during his PhD. Secondly, none of his publications were ever rejected anywhere. This shows that Manil managed to publish in competitive forums in his field and that his work was well-received. Currently, Manil works as a Researcher at Bell Laboratories of Alcatel-Lucent in Belgium. We wish him the best of luck in his future career!