After six days in Munich I have now left the MODELS 2019 conference. It has been an intense couple of days with three days of workshops and tutorials, and three days of main conference. Both the technical and social aspects of the conference were exceptionally well-organized, so kudos to the men and women who worked hard to make that happen.
The four main highlights at the conference for me were:
1. Presenting our paper “Towards Continuous Evolution through Automatic Detection and Correction of Service Incompatibilities” at the MODCOMP workshop. Discussions with conference participants about Petri Net transformations have given inspiration for how to formally work with more complex service behaviors than we do in our work on service-oriented architectures today.
2. A tutorial on StateCharts that improved my understanding of a model-of-computation I will be teaching at the University of Amsterdam in the near future. Thanks to Simon van Mierlo, Hans Vangheluwe, and Axel Terfloth for organizing this tutorial and for sharing their excellent material.
3. Meeting and discussing with representatives from BMW, Daimler, MAN, Continental, TTTech, and other automotive companies and hear more about automotive trends towards centralization of computation, first through domain controllers and then further towards integration of domains in automotive “supercomputers”. It was also interesting to see that the automotive industry is showing interest in service-oriented architectures as a paradigm for their platforms. In fact, a paper entitled “Model-Based Resource Analysis and Synthesis of Service-Oriented Automotive Software Architectures” from BMW got the Best Paper Award on the Practice and Innovation track for work in this direction. This confirms our belief that our current applied research on service-oriented architectures in the defense domain can be generalized to other domains.
4. Meeting and talking to people from both Flanders Make and CETIC, which are the Flemish and Wallonian equivalents of ESI (TNO). It was interesting to talk to them and learn about how what we do is similar and different, both in terms of technical scope and business models.
I hope to return to the MODELS conference again next year to present more of our work and have another opportunity to discuss with and learn from top academics and industrialists in the area of model-based engineering.
Today, Ali presented our Real-time Systems article “Uneven Memory Regulation for Scheduling IMA Applications on Multi-core Platforms” in the Journal-to-conference (J2C) session at ECRTS.
This article addresses the problem of resource sharing in mixed-criticality systems through temporal isolation by extending the state-of-the-art Single-Core Equivalence (SCE) framework in three ways: 1) we extend the theoretical toolkit for the SCE framework by considering EDF and server-based scheduling, instead of partitioned fixed-priority scheduling, 2) we support uneven memory access budgets on a per-server basis, rather than just on a per-core basis, and 3) we formulate an Integer-Linear Programming Model (ILP) guaranteed to find a feasible mapping of a given set of servers to processors, including their execution time and memory access budgets, if such a mapping exists. Our experiments with synthetic task sets confirm that considerable improvement in schedulability can result from the use of per-server memory access budgets under the SCE framework.
Overall, I greatly appreciate that key conferences in the real-time community are starting to allow journal articles to be presented. This increases the exposure of these works that are often longer and better edited. It is also helpful for researchers at the institutes where conference publications are not considered a relevant KPI. You can argue the validity of this reasoning in areas of computer science where conferences are highly competitive with 20-30% acceptance rates, but it is reality for some researchers. An interesting thing with the MODELS conference is that they collaborate with the SOSYM journal such that some accepted articles in the journal gets a full slot at the conference. This is a nice way to highlight good articles and to appreciate the work done by both authors and reviewers.
Our collaboration with CISTER has been extremely fruitful this year, as yet another paper in our research line on mixed-criticality scheduling has been accepted. This latest paper is entitled “Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets” and has been accepted at the International Conference on Embedded Software (EMSOFT).
The goal of this work is, like many other in this research line, is to reduce cost of mixed-criticality systems. This time, we achieve this by addressing the limitation that a server only has a single execution budget in all modes, despite that their computational requirements may vary significantly. More specifically, the three main contributions of the paper are: 1) a scheduling arrangement for uni-processor systems employing fixed-priority scheduling within periodic servers, whose budgets are dynamically adjusted at run-time in the event of a mode change, 2) a new schedulability analysis for such systems, and 3) heuristic algorithms for assigning budgets to servers in different modes and ordering the execution of the servers. Experiments with synthetic task sets demonstrate considerable improvements (up to 52.8%)
I have recently accepted an invitation to speak at the First TCRTS Workshop on Certifiable Multicore Avionics Systems (CMAS), which takes place on April 13 and is co-located with RTAS 2015 in Seattle. The presentation is made in collaboration with Jan Nowotsch at Airbus Group Innovations, where I was a Visiting Researcher during two months last year. The title of the presentation is Towards Certifiable Resource Sharing in Safety-Critical Multi-Core Real-Time Systems and discusses current problems and state-of-the-art methods for resource sharing in real-time multi-core platforms. The abstract of the presentation is found below:
The proliferation of multi-core platforms has had great impact on embedded computing. Multiple cores exploiting task-level parallelism offer performance far beyond what is possible with a single core, while staying within an acceptable power envelope. Since resources, such as interconnect and memories, are often shared between cores, the platforms have also become increasingly cost efficient. However, resource sharing results in interference between concurrently executing applications, which causes problems in real-time systems where such interference must be either bounded or completely eliminated. As a result, safety-critical systems, for example in the avionics domain, have not yet been able to capitalize on the benefits of multi-core platforms due to stringent certification requirements.
This presentation discusses the state-of-the-art in resource sharing in multi-core systems and its application to safety-critical real-time systems. First, a survey of efforts to build time-predictable resources, such as interconnects and memory controllers, is provided. Then, software-based interference mitigation mechanisms and analyses for these resources in commercial-of-the-shelf platforms are discussed. This is followed by an overview of the approach proposed by Airbus Group Innovations to manage interference and compute worst-case execution times of applications running on a Freescale P4080 multi-core platform. The presentation is concluded by highlighting open issues and future directions towards certifiable resource sharing in safety-critical multi-core real-time systems.
Update: The slides are available here.
The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!
The next two weeks involves quite a marketing effort, as I will give three invited presentations about real-time memory controllers in northern, southern, and central Europe, respectively. Tomorrow, I will present our work at the Faculty of Information Technology at Czech Technical University in Prague. On Friday, I will meet with Karl-Erik Arzen and Enrico Bini at the Department of Control at Lund’s Institute of Technology and share my story. Lastly, next week Wednesday, I present at the ReTiS Lab at Scuola Superiore Sant’Anna. I thank all these institutes for the opportunity to present and I hope they will enjoy the story.