ACM Transaction of Embedded Computing Systems (TECS) recently informed us that our article “Maximizing the Number of Good Dies for Streaming Applications in NoC-based MPSoCs under Process Variation” has been accepted for publication. This work nicely summarizes the dissertation of Davit Mirzoyan from his four year PhD studies at Delft University of Technology under the supervision of Kees Goossens and myself.
The article addresses design of real-time systems for streaming applications constrained by a throughput requirement with reduced design margins, referred to as better than worst-case design. The first contribution is a complete modeling framework that captures a streaming application mapped to a NoC-based multiprocessor system with voltage-frequency islands under process-induced die-to-die and within-die frequency variations. The framework is used to analyze the impact of variations in the frequency of hardware components on application throughput at the system level. The second contribution is a methodology to use the proposed framework and estimate the impact of reducing circuit design margins on the number of good dies that satisfy the throughput requirement of a real-time streaming application. It is shown on both synthetic and real applications that the proposed design approach can increase the number of good dies by up to 9.6% and 18.8% for designs with and without fixed SRAM and IO blocks, respectively.
Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems. The article is entitled “A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels” and is an extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel memory controllers in real-time systems.
The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.
ACM Transactions on Embedded Computing Systems (TECS) just accepted our article “Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs”. This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper “Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield”, presented at ISQED in 2012. The camera-ready version is available here.