A paper entitled “Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform” was recently accepted for publication at RTAS. This paper was a collaboration with former colleagues at the CISTER Research Unit, as well as friends from MDH in Sweden. The paper addresses the issue of interference between applications in many-core platforms interconnected using rate-regulated Networks-on-Chip (NoC), such as the Kalray MPPA. The main contributions of the paper are 1) a partitioning strategy for reducing contention on the NoC, 2) an analysis technique to determine the Worst-Case Traversal Time of packages under the proposed strategy, and 3) a method to determine parameters for the NoCs rate regulators to get minimal WCTT and ensure that buffers never overflow. The benefits of the proposed approach is evaluated both using simulation and by experiments on a Kalray MPPA. Furthermore, an industrial case study from the automotive domain shows the tightness of the proposed analysis.
Today we celebrate that the Memory Team had both papers submitted to DATE accepted as full papers at the conference. The first paper was written by Manil Dev Gomony and is entitled “Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems”. This paper discusses area, power and performance benefits of coupling the arbitration in a TDM NoC with the memory controller arbitration, thereby reducing the number of arbitration points on the path from processor to memory. The second paper entitled “Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization” was first-authored by Karthik Chandrasekar. This paper shows how to exploit excessive process margins in DRAMs by proposing a methodology for how to determine the minimum timings that a memory can safely run at, thereby improving performance.