Bachelor Thesis on Synthetic Interface Generation Defended

Mohammed (Mo) Diallo just defended his bachelor thesis entitled “Towards the Scalability of Detecting and Correcting Incompatible Service Interfaces“. This work is carried out in the context of a project between ESI (TNO) and Thales that developed a five-step methodology for automatic detection and correction of behavioral incompatibilities resulting from evolving software interfaces (see paper for more details). Mo’s thesis provides a starting point for evaluating the scalability of the proposed methodology. An essential ingredient towards this is the ability to synthetically generate interfaces of various complexity. The thesis has two main contributions: 1) a notion of interface complexity in terms of inputs, outputs and non-determinism is defined and the relation between these parameters is studied, and 2) the methodology for a ComMA interface generator using user-supplied complexity parameters, and its implementation in a supporting tool, is introduced.

I would like to thank Mo for the excellent work he delivered in this thesis, and I am happy that he will continue working over summer to extend it.

DRAMPower v4.0 Released!

A new version of the DRAMPower tool has been released. The two main features of version 4 are:

  1. DRAMPower can now be compiled as a library. This enables a user to access the tool through an API and log commands and their corresponding time stamps, removing the need to store large command traces on disk. The key benefit of this feature is that users can easily integrate DRAMPower into their own memory controller simulators and obtain power and energy consumption estimates. In fact, this version of DRAMPower is already integrated into the memory controller of the gem5 simulator system and is provided with the latest release.
  2. Improved robustness. The latest build is checked out every night on a test server, compiled, and tested to verify that the output matches an expected reference for a battery of tests. The code is also compiled with a large number of warning flags enabled and treats all warnings as errors. This feature makes it easier for the community to reliably contribute to the tool, which is now possible through github.

Check it out the new version of DRAMPower here.

RTMemController v1.0 Released

The Memory Team is proud to release another open-source tool to the community. This tool is called RTMemController and contains a mathematical formalization of the dynamic command scheduler introduced in Yonghui Li’s paper Dynamic Command Scheduling for Real-Time Memory Controllers that will be presented at ECRTS. The tool is capable of determining worst-case and average-case execution times of memory transactions of different transaction sizes and with varying degrees of bank interleaving.

An important driver for releasing this tool is to promote transparency and fair comparisons between work in the field. Longer term development plans for the tool may involve adding support for a memory controller front-end with different transaction schedulers, adding support for more memory generations (currently DDR3 is supported), and making the output compatible with DRAMPower to enable chaining the tools.

The official website of RTMemController is found here. Also check out the paper that describes the scheduling algorithm and its formalization.

DRAMPower v3.1 Released!

The latest version of the tool now includes IO and Termination power measures from Micron’s DRAM Power Calculator for all supported DRAM generations. This feature enables support for power estimation of dual-rank DRAMs (DDR2/3/4). Additionally, new warning messages have been added, to identify if the memory or bank state is inconsistent in the user-defined command traces. This release also fixes minor bugs related to Precharge All (PREA) to improve the accuracy of DRAM power estimation.

Check it out here.

DRAMPower v3.0 Released!

DRAMPower v3.0 has been released! The tool can now be employed with two interfaces: (1) Command traces and (2) Transaction traces (new feature). To facilitate usage of memory transaction traces, DRAMPower now includes an optional DRAM command scheduler, which dynamically schedules and logs DRAM commands, corresponding to the incoming memory transactions, as if it was connected to a memory controller. The scheduler assumes a closed-page policy, employs FCFS scheduling across transactions and uses ASAP scheduling for DRAM commands. This release also adds support for DDR4 and LPDDR3 devices and fixes minor bugs to improve the accuracy of DRAM power estimation. Click here to check it out.

DRAMPower v2.1 is Available and Variation-aware

The DRAMPower tool has been updated to v2.1 with support for variation-aware power estimation for a selection of DDR3 memories, based on the analysis presented in our DAC ’13 article. Towards this, 15 sample datasheets reflecting the impact of process-variations on DRAM currents have been added to tool.

For more information, or to download the tool, please refer to the official DRAMPower website.

DRAMPower v2.0 Released!

The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements, such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories. The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations, which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.

For more information, or to download the tool, please refer to the official DRAMPower website.