Today, Manil Dev Gomony has successfully defended his PhD thesis entitled “Scalable and Bandwidth-Efficient Memory Subsystem Design for Real-Time Systems“. The thesis proposes an architecture for a real-time memory subsystem that scales well in terms of area and maximum synthesizable frequency with an increasing number of memory clients. This subsystem architecture comprises a memory interconnect called Globally Arbitrated Memory Tree (GAMT) a Multi-Channel Memory Controller (MCMC), as well as a technique to couple those components and have a single point of arbitration for both resources. The thesis also proposes a design flow for automatically choosing the memory device, mapping clients to memory channel, and configure arbiters to satisfy client requirements.
Among Manil’s achievements, we specifically highlight two achievements with respect to publishing. First of all, he had a paper accepted at the DATE conference every year during his PhD. Secondly, none of his publications were ever rejected anywhere. This shows that Manil managed to publish in competitive forums in his field and that his work was well-received. Currently, Manil works as a Researcher at Bell Laboratories of Alcatel-Lucent in Belgium. We wish him the best of luck in his future career!
Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems. The article is entitled “A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels” and is an extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel memory controllers in real-time systems.
The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.
The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:
The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.