Sven Goossens Successfully Defended Dissertation

After successfully defending his dissertation “A Reconfigurable Mixed-Time-Criticality SDRAM Controller“, Sven Goossens earned himself a PhD degree and the right to call himself a doctor. The work proposes a pattern-based SDRAM controller targeting mixed-time-criticality systems, i.e. systems where some memory clients need firm worst-case guarantees on bandwidth and latency, while other clients only care about average-case performance. A new memory controller architecture is designed to address this mix of requirements and it is implemented both as a cycle-accurate SystemC simulation model and as synthesizable RTL code for generating FPGA instances. A unique feature of this memory controller is its conservative open-page policy that leaves rows open in the memory banks as long as possible to exploit locality and boost average-case performance, but closes them just in time to avoid reducing the worst-case performance.

The work also parameterizes the concept of memory patterns by allowing the number of banks and the number of bursts per bank to be chosen when the patterns are generated. This allows patterns with different degrees of bank-level parallelism to be created for six different generations of DRAM for any request size, enabling the user to make a trade-off between worst-case bandwidth, worst-case response time, and power consumption. To generate efficient memory patterns, the work proposes an integer linear programming formulation that provides optimal patterns, as well as a near-optimal heuristic that runs in a fraction of the time. In addition to generating predictable memory patterns that provide bounded bandwidth and execution times, composable read and write patterns can be generated with negligible performance loss. These patterns have equal length and can be used to provide complete temporal isolation between memory clients when combined with a non-work-conserving Time-Division Multiplexing (TDM) arbiter in the front-end. The memory patterns are generated offline at design time, but are programmed at run-time when the memory controller is initialized. Lastly, the proposed controller supports run-time reconfiguration of its TDM arbiter, allowing it to be safely reprogrammed when applications dynamically start and stop at run-time without sacrificing the worst-case guarantees of applications that keep running.

I would like to thank Sven for the five years of hard work. It has been a pleasure to work with such a versatile and independent young researcher who seems to be succesful at whatever he attempts, be it design, analysis, writing papers, or hardware/software implementation in more or lesss any language. He has also been an excellent member of the Memory Team and the larger CompSoC Team, never passing on an opportunity to use his skills to support other members of the team. At the end of January, Sven starts his new career with Intrinsic-ID in Eindhoven. We wish him the best of luck with his new job and hope to stay in touch.

Three Presentations at ESWEEK

The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!

Accepted Paper at CODES/ISSS 2013

Our paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” has been accepted at CODES/ISSS 2013. The paper is first-authored by Sven Goossens and builds on the work of Jasper Kuijsten, a graduated master student from the Memory Team. In this paper, we present a new architecture of our real-time memory controller that supports predictable and composable run-time reconfiguration on use-case transitions, which allows trade-offs between guaranteed bandwidth, response time and power. It also presents a methodology for offering composable service to memory clients by means of composable memory patterns, an extension to our existing pattern-based approach. Lastly, a reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol are proposed. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA platform.

Jasper Kuijsten Graduates from the Memory Team

Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.