Tag: process variation

ACM TECS Accepts Another Journal Article

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ACM Transaction of Embedded Computing Systems (TECS) recently informed us that our article “Maximizing the Number of Good Dies for Streaming Applications in NoC-based MPSoCs under Process Variation” has been accepted for publication. This work nicely summarizes the dissertation of Davit Mirzoyan from his four year PhD studies at Delft University of Technology under the supervision of Kees Goossens and myself.

The article addresses design of real-time systems for streaming applications constrained by a throughput requirement with reduced design margins, referred to as better than worst-case design. The first contribution is a complete modeling framework that captures a streaming application mapped to a NoC-based multiprocessor system with voltage-frequency islands under process-induced die-to-die and within-die frequency variations. The framework is used to analyze the impact of variations in the frequency of hardware components on application throughput at the system level. The second contribution is a methodology to use the proposed framework and estimate the impact of reducing circuit design margins on the number of good dies that satisfy the throughput requirement of a real-time streaming application. It is shown on both synthetic and real applications that the proposed design approach can increase the number of good dies by up to 9.6% and 18.8% for designs with and without fixed SRAM and IO blocks, respectively.

First PhD Student Graduates From the Memory Team

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Today, Karthik Chandrasekar was promoted to doctor as he confidently defended his PhD thesis “High-Level Power Estimation and Optimization of DRAMs”. The thesis proposes a high-level power estimation tool called DRAMPowerthat estimates the power and energy consumption of different generations of DRAMs based on a memory command trace and current values from the memory datasheet. Since current numbers in datasheets are often pessimistic for a majority of the manufactured memory devices, a methodology is also proposed to characterize DRAM modules post-manufacturing to achieve more accurate power and performance estimates for the characterized devices. Lastly, the thesis discusses power optimization in the context of real-time memory controllers and proposes two power-down strategies to reduce the power consumption of memories in real-time systems without sacrificing worst-case performance.

The defense went very well and the committee was particularly pleased with how the DRAMPower tool was verified using measurements on real hardware and how it has attracted interest from industry. Karthik is the first PhD student to graduate from the Memory Team and the rest of the team wishes him all the best for his future career at Nvidia.

Davit Mirzoyan Successfully Defends PhD Thesis!

Posted on by bennyakesson

On this day, Davit Mirzoyan confidently defended his PhD thesis, earning the right to call himself a doctor. The thesis is entitled Better than Worst-Case Design for Streaming Applications under Process Variation and discusses how process variation during chip manufacturing can be exploited during application mapping and voltage-frequency island partitioning to increase the number of chips that satisfy the real-time requirements of the application. The work is very interesting, as it captures how variation in transistor parameters affect application performance, thus tying together the lowest and the highest levels of system design.

An interesting fact is that due to circumstances beyond Davits control, he had to write his thesis and send it off to the committee in only two months, something most people would not be able to do, yet he delivered a nice piece of work that was referred to as a ‘very smooth read’ by the committee. As Davits co-promotor, I am very proud of his achievement and I have very much enjoyed working with him during the past four years. I wish him the best of luck in his future career.

Two Papers Accepted at DATE 2014

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Today we celebrate that the Memory Team had both papers submitted to DATE accepted as full papers at the conference. The first paper was written by Manil Dev Gomony and is entitled “Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems”. This paper discusses area, power and performance benefits of coupling the arbitration in a TDM NoC with the memory controller arbitration, thereby reducing the number of arbitration points on the path from processor to memory. The second paper entitled “Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization” was first-authored by Karthik Chandrasekar. This paper shows how to exploit excessive process margins in DRAMs by proposing a methodology for how to determine the minimum timings that a memory can safely run at, thereby improving performance.

Three Presentations at ESWEEK

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The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!

Accepted Paper at ESTIMedia 2013

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To our great delight, Davit Mirzoyan’s paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” has been accepted at ESTIMedia 2013. The paper extends his earlier work and presents a framework to estimate the probability distribution of application throughput (e.g. frames per second in video decoding) in a system with Voltage-Frequency Island (VFI) partitions in the presence of process variation. The novelty of the framework lies in the computation of the probability distribution of throughput, based on a user-specified set of clock-frequency levels per VFI domain considering both within-die and die-to-die variations of cores. A methodology is furthermore provided to perform variation-aware partitioning of the cores of a MPSoC into VFIs for maximized timing yield (percentage of chips that satisfy a given throughput requirement).

DRAMPower v2.1 is Available and Variation-aware

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The DRAMPower tool has been updated to v2.1 with support for variation-aware power estimation for a selection of DDR3 memories, based on the analysis presented in our DAC ’13 article. Towards this, 15 sample datasheets reflecting the impact of process-variations on DRAM currents have been added to tool.

For more information, or to download the tool, please refer to the official DRAMPower website.

Article about Variation-aware Mapping Accepted by ACM TECS

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ACM Transactions on Embedded Computing Systems (TECS) just accepted our article “Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs”. This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper “Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield”, presented at ISQED in 2012. The camera-ready version is available here.

Paper Accepted at DAC 2013

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For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.

Update: The paper is now available online. Click here to read it.