Author: bennyakesson

Paper Accepted at RTCSA 2013

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Today, we congratulate Hazem Ali for having his first paper accepted at RTCSA. The paper is entitled “Critical-Path-First Based Allocation of Real-Time Streaming Applications on 2D Mesh-Type Multi-Cores” and proposes a mapping strategy for streaming applications, represented as acyclic data-flow graphs with throughput requirements, to multi-core architectures under partitioned EDF scheduling. The key idea is to first map tasks on the critical-paths of the application to minimize their execution time and thereby increasing the chance to satisfy the throughput constraint. The camera-ready version is available here.

Hazem Ali is a PhD student at the CISTER-ISEP Research Unit in Porto, supervised by Luis Miguel Pinho and myself, and this paper is a result of my six month visit there last year and the fruitful collaboration it has resulted in afterwards.

Article about Variation-aware Mapping Accepted by ACM TECS

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ACM Transactions on Embedded Computing Systems (TECS) just accepted our article “Process-Variation Aware Mapping of Best-Effort and Real-Time Streaming Applications to MPSoCs”. This work discusses how to efficiently map streaming applications, represented as synchronous data-flow graphs, with different types of real-time requirements to multi-processor systems affected by process variation (maximum frequencies of each processor follows a statistical distribution). The main goal is to map the tasks of the applications to the system in such a way that the probability of satisfying the real-time requirements of the applications is maximized. This work is an extension of the conference paper “Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield”, presented at ISQED in 2012. The camera-ready version is available here.

Paper Accepted at SIES 2013

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A paper entitled “Identifying the Sources of Unpredictability in COTS-based Multicore Systems” was accepted at SIES 2013. This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.

Update: The paper is now available online here.

DRAMPower v2.0 Released!

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The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements, such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories. The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations, which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.

For more information, or to download the tool, please refer to the official DRAMPower website.

Paper Accepted at DAC 2013

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For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.

Update: The paper is now available online. Click here to read it.

Back in Eindhoven

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After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.

Jasper Kuijsten Graduates from the Memory Team

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Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.

HiPEAC Membership

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I have recently become a member of the HiPEAC Network of Excellence, a network with the goal to steer and increase the European research in the area of high-performance and embedded computing systems and to stimulate collaboration between academia and industry. Joining this network is an additional step towards establishing a strong international network and I look forward to meeting new interesting people as well as seeing some well-known faces at future HiPEAC events. The membership also provides interesting collaboration opportunities by providing collaboration grants to PhD students. Any PhD students interested in a three-month collaboration visit in Prague is welcome to contact me to discuss if there is any interesting work we can do together that can result in a high-quality joint publication.

Successful Collaboration Lands Paper at PADL 2013

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Another successful collaboration has resulted in an accepted publication at the Fifteenth International Symposium on Practical Aspects of Declarative Languages (PADL). The title of the paper is “A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction” and it was written together with Vitor Rodrigues, Simão Melo de Sousa, and Mário Florido from Universidade do Porto and Universidade da Beira Interior. The paper discusses the theory and declarative implementation of timing analysis for multi-cores using abstract interpretation. To manage the state-space explosion of possible interleavings of requests from different cores to shared resources, the latency-rate abstraction is proposed and proven to be sound in the context of the proposed analysis. The resulting loss of precision is then evaluated for a simple system where a memory is shared using TDM arbitration.

Memory Team Scores Four out of Four Accepted Papers at DATE 2013!

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The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:

The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.