Optimizing Efficiency and Performance: PhD Thesis Defense on Energy- and Time-aware Scheduling for High-Performance Embedded Systems

Yesterday, I participated in the PhD defense committee of Julius Röder, a PhD student in the Parallel Computing Systems group at the University of Amsterdam. The thesis “Energy- and Time-aware Scheduling for Heterogeneous High-Performance Embedded Systems” addresses the relevant problem of optimizing non-functional behavior, such as timing and energy consumption, of heterogeneous high-performance embedded systems. The goal of this optimization Is to reduce energy consumption, thereby also reducing carbon footprint and extending battery-life, as well as ensuring that real-time requirements of applications are satisfied, even at high resource utilizations. To this end, the thesis contributes a discussion on setups used for energy measurements, as well as experiments and a statistical analysis that demonstrate the Importance of sampling frequency on the accuracy of such measurements. The bulk of the thesis proposes heuristic algorithms, both conventional and based on reinforcement learning, for mapping and scheduling applications modelled as directed acyclic graphs (DAG) on heterogeneous platforms. The applications are assumed to be available In different versions, with different non-functional behavior, for the different types of processing elements In the heterogeneous architecture, which enables trade-offs between timing and energy. A key strength of the thesis is that theory is combined with a practical component; the scheduling algorithms are implemented and evaluated on a heterogeneous multi-core systems, where timing and energy behavior are carefully measured and analyzed.

In presence of family, friends, and colleagues, Julius confidently defended his PhD thesis and earned the right to call himself a doctor. Congratulations Julius with this great achievement!

New Book Available for Pre-order

Our new book “Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-offs” is now available for pre-order at Springer. The book is based on the excellent PhD thesis of Sven Goossens and discusses the design and FPGA implementation of a real-time memory controller for mixed-criticality systems. The controller can provide complete temporal isolation to its clients as well as hard bounds on the worst-case response time of transactions and the bandwidth offered by the memory. In addition, it provides competitive average-case performance for soft real-time and best-effort applications using a conservative open-page policy. The design is highly configurable and the book carefully quantifies the trade-offs between bandwidth, response time, and power that this enables. To facilitate the discussion about power, the book also presents the power model that came out of the PhD dissertation of Karthik Chandrasekar and gives an up-to-date description of the open-source DRAMPower tool that implements it.

Update: The contents of the book are now available on SpringerLink

First PhD Student Graduates From the Memory Team

Today, Karthik Chandrasekar was promoted to doctor as he confidently defended his PhD thesis “High-Level Power Estimation and Optimization of DRAMs”. The thesis proposes a high-level power estimation tool called DRAMPowerthat estimates the power and energy consumption of different generations of DRAMs based on a memory command trace and current values from the memory datasheet. Since current numbers in datasheets are often pessimistic for a majority of the manufactured memory devices, a methodology is also proposed to characterize DRAM modules post-manufacturing to achieve more accurate power and performance estimates for the characterized devices. Lastly, the thesis discusses power optimization in the context of real-time memory controllers and proposes two power-down strategies to reduce the power consumption of memories in real-time systems without sacrificing worst-case performance.

The defense went very well and the committee was particularly pleased with how the DRAMPower tool was verified using measurements on real hardware and how it has attracted interest from industry. Karthik is the first PhD student to graduate from the Memory Team and the rest of the team wishes him all the best for his future career at Nvidia.

DRAMPower v3.1 Released!

The latest version of the tool now includes IO and Termination power measures from Micron’s DRAM Power Calculator for all supported DRAM generations. This feature enables support for power estimation of dual-rank DRAMs (DDR2/3/4). Additionally, new warning messages have been added, to identify if the memory or bank state is inconsistent in the user-defined command traces. This release also fixes minor bugs related to Precharge All (PREA) to improve the accuracy of DRAM power estimation.

Check it out here.

DRAMPower v3.0 Released!

DRAMPower v3.0 has been released! The tool can now be employed with two interfaces: (1) Command traces and (2) Transaction traces (new feature). To facilitate usage of memory transaction traces, DRAMPower now includes an optional DRAM command scheduler, which dynamically schedules and logs DRAM commands, corresponding to the incoming memory transactions, as if it was connected to a memory controller. The scheduler assumes a closed-page policy, employs FCFS scheduling across transactions and uses ASAP scheduling for DRAM commands. This release also adds support for DDR4 and LPDDR3 devices and fixes minor bugs to improve the accuracy of DRAM power estimation. Click here to check it out.

DRAMPower v2.1 is Available and Variation-aware

The DRAMPower tool has been updated to v2.1 with support for variation-aware power estimation for a selection of DDR3 memories, based on the analysis presented in our DAC ’13 article. Towards this, 15 sample datasheets reflecting the impact of process-variations on DRAM currents have been added to tool.

For more information, or to download the tool, please refer to the official DRAMPower website.

DRAMPower v2.0 Released!

The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements, such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories. The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations, which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.

For more information, or to download the tool, please refer to the official DRAMPower website.

Paper Accepted at DAC 2013

For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.

Update: The paper is now available online. Click here to read it.

Paper Accepted at ESTIMedia 2012

Andrew Nelson just had a paper “Power Versus Quality Trade-offs for Adaptive Real-Time Applications” accepted at ESTIMedia 2012. The paper is based on the work of Sjoerd te Pas, one of my graduated master students, and discusses how power consumption can be traded for application quality for adaptive real-time applications using existing DVFS techniques. The techniques are demonstrated for an H.263 application on an FPGA instance of the CompSOC platform. Stay tuned for the camera-ready version.

Update: The paper is now available online. Click here to read it.