H2020 Project HERCULES in Grant Agreement Preparation

The European Commission just notified us that our H2020 IA project HERCULES (High-pErformance Real-time arChitectUres for Low-power Embedded Systems) has reached the stage of grant agreement preparation. Earlier this year, I took the lead on this proposal on behalf of CTU Prague and also contributed more generally to the preparation. Given the competitive nature of H2020, I am pleased to see that the work was well received. A particular congratulations to Marko Bertogna and his team at University of Modena for their hard work on coordinating this proposal. Now let’s hope the negotiation phase goes well!

Project HERCULES has the ambitious goal to provide the required technological infrastructure to obtain an order-of-magnitude improvement in the cost and power consumption of next generation real-time applications. It will develop an integrated framework to allow achieving predictable performance on top of cutting-edge heterogeneous COTS multi-core platforms, implementing real-time scheduling techniques and execution models recently proposed in the research community. The framework will be applied to two innovative industrial use cases: a pioneering autonomous driving system for the automotive domain, and a visual recognition system for the avionic domain.

Article Accepted in IEEE Transactions on Computer

The spree of accepted journal articles continues as Sven Goossens’ article entitled “Power/Performance Trade-offs in Real-Time SDRAM Command Scheduling” was accepted for publication in IEEE Transactions on Computers. The article contains a detailed discussion about the trade-offs between bandwidth, execution time, and power when DRAM requests are scheduled by a real-time memory controller under a close-page policy. The results cover a wide range of memories ranging from DDR2/3/4 to LPDDR1/2/3 for different request sizes and amounts of bank parallelism. Other key contributions of the article are: 1) publicly available heuristic and optimal algorithms for generation of memory patters that covers all aforementioned memories, 2) a simple abstraction that quickly captures the differences between the different DRAM generations allowing algorithms and analyses to be easily adapted to cover all of them, and 3) a pairwise bank-group interleaving scheme for DDR4 that exploits bank grouping for improved performance.

DRAMPower v2.0 Released!

The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements, such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories. The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations, which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.

For more information, or to download the tool, please refer to the official DRAMPower website.

Paper Accepted at DSD 2012

The memory team congratulates Gervin Thomas from TU Berlin for having his paper entitled “A Predictor-based Power-Saving Policy for DRAM Memories” accepted at DSD 2012. This work is the result of Gervin’s HiPEAC collaboration visit in Eindhoven between August and October 2011. During this time, he worked closely with Karthik Chandrasekar on finding a way to use the self-refresh mode of DRAMs to reduce the power consumption in soft real-time systems without significantly reducing performance. The camera-ready version of the paper will be available shortly.

Update: The paper is now available online. Click here to read it.

Paper Accepted at DAC 2012

Today, we congratulate Karthik Chandrasekar on getting his paper “Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers” accepted at Design Automation Conference (DAC) 2012, where it will be presented in early June. The paper proposes two run-time power down strategies for real-time SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy is conservative and saves power without affecting latency, whereas the second is more aggressive and saves additional power at a slightly increased latency. The paper also presents an algorithm to select the most energy-efficient power-down mode at run-time.

Update: The camera-ready version is now available. Click here to download it.