For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.
Update: The paper is now available online. Click here to read it.
Today, we congratulate Karthik Chandrasekar on getting his paper “Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers” accepted at Design Automation Conference (DAC) 2012, where it will be presented in early June. The paper proposes two run-time power down strategies for real-time SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy is conservative and saves power without affecting latency, whereas the second is more aggressive and saves additional power at a slightly increased latency. The paper also presents an algorithm to select the most energy-efficient power-down mode at run-time.
Update: The camera-ready version is now available. Click here to download it.