H2020 Project HERCULES in Grant Agreement Preparation

The European Commission just notified us that our H2020 IA project HERCULES (High-pErformance Real-time arChitectUres for Low-power Embedded Systems) has reached the stage of grant agreement preparation. Earlier this year, I took the lead on this proposal on behalf of CTU Prague and also contributed more generally to the preparation. Given the competitive nature of H2020, I am pleased to see that the work was well received. A particular congratulations to Marko Bertogna and his team at University of Modena for their hard work on coordinating this proposal. Now let’s hope the negotiation phase goes well!

Project HERCULES has the ambitious goal to provide the required technological infrastructure to obtain an order-of-magnitude improvement in the cost and power consumption of next generation real-time applications. It will develop an integrated framework to allow achieving predictable performance on top of cutting-edge heterogeneous COTS multi-core platforms, implementing real-time scheduling techniques and execution models recently proposed in the research community. The framework will be applied to two innovative industrial use cases: a pioneering autonomous driving system for the automotive domain, and a visual recognition system for the avionic domain.

Paper Accepted at SIES 2013

A paper entitled “Identifying the Sources of Unpredictability in COTS-based Multicore Systems” was accepted at SIES 2013. This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.

Update: The paper is now available online here.

Jasper Kuijsten Graduates from the Memory Team

Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.