Category: Publications

Paper Accepted at DAC 2013

Posted on by bennyakesson

For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.

Update: The paper is now available online. Click here to read it.

Successful Collaboration Lands Paper at PADL 2013

Posted on by bennyakesson

Another successful collaboration has resulted in an accepted publication at the Fifteenth International Symposium on Practical Aspects of Declarative Languages (PADL). The title of the paper is “A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction” and it was written together with Vitor Rodrigues, Simão Melo de Sousa, and Mário Florido from Universidade do Porto and Universidade da Beira Interior. The paper discusses the theory and declarative implementation of timing analysis for multi-cores using abstract interpretation. To manage the state-space explosion of possible interleavings of requests from different cores to shared resources, the latency-rate abstraction is proposed and proven to be sound in the context of the proposed analysis. The resulting loss of precision is then evaluated for a simple system where a memory is shared using TDM arbitration.

Memory Team Scores Four out of Four Accepted Papers at DATE 2013!

Posted on by bennyakesson

The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:

The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.

Paper Accepted at ESTIMedia 2012

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Andrew Nelson just had a paper “Power Versus Quality Trade-offs for Adaptive Real-Time Applications” accepted at ESTIMedia 2012. The paper is based on the work of Sjoerd te Pas, one of my graduated master students, and discusses how power consumption can be traded for application quality for adaptive real-time applications using existing DVFS techniques. The techniques are demonstrated for an H.263 application on an FPGA instance of the CompSOC platform. Stay tuned for the camera-ready version.

Update: The paper is now available online. Click here to read it.

Paper Accepted at DSD 2012

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The memory team congratulates Gervin Thomas from TU Berlin for having his paper entitled “A Predictor-based Power-Saving Policy for DRAM Memories” accepted at DSD 2012. This work is the result of Gervin’s HiPEAC collaboration visit in Eindhoven between August and October 2011. During this time, he worked closely with Karthik Chandrasekar on finding a way to use the self-refresh mode of DRAMs to reduce the power consumption in soft real-time systems without significantly reducing performance. The camera-ready version of the paper will be available shortly.

Update: The paper is now available online. Click here to read it.

Paper Accepted at DAC 2012

Posted on by bennyakesson

Today, we congratulate Karthik Chandrasekar on getting his paper “Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers” accepted at Design Automation Conference (DAC) 2012, where it will be presented in early June. The paper proposes two run-time power down strategies for real-time SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy is conservative and saves power without affecting latency, whereas the second is more aggressive and saves additional power at a slightly increased latency. The paper also presents an algorithm to select the most energy-efficient power-down mode at run-time.

Update: The camera-ready version is now available. Click here to download it.