Paper Accepted at DAC 2012

Today, we congratulate Karthik Chandrasekar on getting his paper “Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers” accepted at Design Automation Conference (DAC) 2012, where it will be presented in early June. The paper proposes two run-time power down strategies for real-time SDRAM controllers that reduce power without sacrificing guaranteed bandwidth. One strategy is conservative and saves power without affecting latency, whereas the second is more aggressive and saves additional power at a slightly increased latency. The paper also presents an algorithm to select the most energy-efficient power-down mode at run-time.

Update: The camera-ready version is now available. Click here to download it.