We just had a paper accepted at the Real-Time and Embedded Technology and Applications Symposium (RTAS) in Seattle. The paper is entitled “An Efficient Configuration Methodology for Time-Division Multiplexed Single Resources” and presents an ILP-based methodology to allocate TDM slots to resource clients, such that bandwidth and latency constraints are satisfied while resource utilization is minimized. A heuristic algorithm is furthermore proposed to determine the number of TDM slots in the schedule. This paper is a collaboration both with colleagues here at CTU Prague and with Andrew Nelson from Eindhoven University of Technology.
For the camera-ready version of the paper, please click here.
The notifications from the DATE conference are in and the Memory Team scores 2 out of 2, just like in 2014. The first paper entitled “A Generic, Scalable and Globally Arbitrated Memory Tree for Shared DRAM Access in Real-Time Systems” was first-authored by Manil and is a collaboration with Jamie Garside and Neil Audsley from University of York. The paper proposes a memory interconnect for shared memory architectures in many-core systems. A main architectural feature is that the interconnect is heavily pipelined enabling it to be synthesized at high frequencies even with a large number of clients. Another highlight is that it has global arbitration that can be programmed to behave like several different arbitration mechanisms, such as TDM, CCSP and FBSP.
The second paper “Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs”was first-authored by our colleagues at Kaiserslautern University of Technology in collaboration with Sven Goossens from our Memory Team. This paper looks into the thermal behavior of 3D-stacked WIDE I/O DRAM and compares its impact on retention time and bit error rates to conventional 2D DRAM chips.
A new version of the DRAMPower tool has been released. The two main features of version 4 are:
- DRAMPower can now be compiled as a library. This enables a user to access the tool through an API and log commands and their corresponding time stamps, removing the need to store large command traces on disk. The key benefit of this feature is that users can easily integrate DRAMPower into their own memory controller simulators and obtain power and energy consumption estimates. In fact, this version of DRAMPower is already integrated into the memory controller of the gem5 simulator system and is provided with the latest release.
- Improved robustness. The latest build is checked out every night on a test server, compiled, and tested to verify that the output matches an expected reference for a battery of tests. The code is also compiled with a large number of warning flags enabled and treats all warnings as errors. This feature makes it easier for the community to reliably contribute to the tool, which is now possible through github.
Check it out the new version of DRAMPower here.
Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems. The article is entitled “A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels” and is an extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel memory controllers in real-time systems.
The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.
Today, we congratulate Yonghui Li on an accepted paper at ECRTS. The paper is entitled Dynamic Command Scheduling for Real-Time Memory Controllers and presents both an architecture and analysis for a dynamically scheduled SDRAM controller supporting different transaction sizes and memory map configurations. This is Yonghui’s first accepted paper and we are proud to see that it got very good reviews from one of the most competitive conferences in the field. Now the work begins on preparing a camera-ready version and making the scheduling algorithm publicly available for comparisons in community.
The latest version of the tool now includes IO and Termination power measures from Micron’s DRAM Power Calculator for all supported DRAM generations. This feature enables support for power estimation of dual-rank DRAMs (DDR2/3/4). Additionally, new warning messages have been added, to identify if the memory or bank state is inconsistent in the user-defined command traces. This release also fixes minor bugs related to Precharge All (PREA) to improve the accuracy of DRAM power estimation.
Check it out here.
A paper about the CompSOC tool-flow has been accepted that describes the highly automated effort of specifying and creating instances of the CompSOC platform, map applications to resources considering their real-time requirements, and executing the resulting system on FPGA. Three sub-flows of the tool-flow and their interactions are briefly explained: 1) the hardware tool flow, capable of translating a high-level description of a CompSOC platform instance into a fully synthesized implementation, 2) A system software flow, generating a software stack including a composable micro kernel, resource managers, drivers, and a virtual platform boot loader, and 3) An application flow that automatically generates a virtual platform configuration for applications that use the Cyclo-static Data Flow (CSDF) model of computation. The paper will be presented at FPGAworld and puts particular emphasis on practical aspects related to the first of these sub-flows and on the interaction with tools for our FPGA target.
The new version of our tool for fast and accurate system-level power estimation of DRAMs has been released. This version features many important improvements, such as significantly improved analysis speed (at least 10x), enabling analysis of much larger traces, as well as support for LPDDR/LPDDR2 and Wide I/O memories. The results of this version have furthermore been verified by Kaiserslautern University of Technology using equivalent circuit-level SPICE simulations, which established that the error of the tool is < 2% for all memory operations of any granularity for all memories supported by DRAMPower.
For more information, or to download the tool, please refer to the official DRAMPower website.
After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.
The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:
The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.