The next two weeks involves quite a marketing effort, as I will give three invited presentations about real-time memory controllers in northern, southern, and central Europe, respectively. Tomorrow, I will present our work at the Faculty of Information Technology at Czech Technical University in Prague. On Friday, I will meet with Karl-Erik Arzen and Enrico Bini at the Department of Control at Lund’s Institute of Technology and share my story. Lastly, next week Wednesday, I present at the ReTiS Lab at Scuola Superiore Sant’Anna. I thank all these institutes for the opportunity to present and I hope they will enjoy the story.
Jasper Kuijsten Graduates from the Memory Team
Another master student has graduated from the Memory Team. Jasper Kuijsten joined the team in March 2012 and has worked on predictable and composable reconfiguration of the memory controller front-end. His work has been very diverse and contains theoretical comparisons between different approaches to composability in terms of efficiency and reconfiguration effort, but also implementation of his concepts and ideas in both SystemC and VHDL. The Memory Team thanks Jasper for his hard work and good team spirit during the project and wishes him the best of luck in his future career.
Memory Team Scores Four out of Four Accepted Papers at DATE 2013!
The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:
- Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers
- Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis
- System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
- Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller
The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.