Visiting Researcher at Airbus Group Innovations

Today, I start a two month stay as Visiting Researcher at Airbus Group Innovations in Ottobrunn, Germany. I will be working together with Jan Nowotsch on topics related to performance analysis of memory accesses in COTS multi-core platforms. During my stay, I look forward to meeting new people learning more about real-time systems in the avionics domain.

DRAMPower v4.0 Released!

A new version of the DRAMPower tool has been released. The two main features of version 4 are:

  1. DRAMPower can now be compiled as a library. This enables a user to access the tool through an API and log commands and their corresponding time stamps, removing the need to store large command traces on disk. The key benefit of this feature is that users can easily integrate DRAMPower into their own memory controller simulators and obtain power and energy consumption estimates. In fact, this version of DRAMPower is already integrated into the memory controller of the gem5 simulator system and is provided with the latest release.
  2. Improved robustness. The latest build is checked out every night on a test server, compiled, and tested to verify that the output matches an expected reference for a battery of tests. The code is also compiled with a large number of warning flags enabled and treats all warnings as errors. This feature makes it easier for the community to reliably contribute to the tool, which is now possible through github.

Check it out the new version of DRAMPower here.

First PhD Student Graduates From the Memory Team

Today, Karthik Chandrasekar was promoted to doctor as he confidently defended his PhD thesis “High-Level Power Estimation and Optimization of DRAMs”. The thesis proposes a high-level power estimation tool called DRAMPowerthat estimates the power and energy consumption of different generations of DRAMs based on a memory command trace and current values from the memory datasheet. Since current numbers in datasheets are often pessimistic for a majority of the manufactured memory devices, a methodology is also proposed to characterize DRAM modules post-manufacturing to achieve more accurate power and performance estimates for the characterized devices. Lastly, the thesis discusses power optimization in the context of real-time memory controllers and proposes two power-down strategies to reduce the power consumption of memories in real-time systems without sacrificing worst-case performance.

The defense went very well and the committee was particularly pleased with how the DRAMPower tool was verified using measurements on real hardware and how it has attracted interest from industry. Karthik is the first PhD student to graduate from the Memory Team and the rest of the team wishes him all the best for his future career at Nvidia.

Article in ACM Transactions on Embedded Computing Systems (TECS)

Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems. The article is entitled “A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels” and is an extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel memory controllers in real-time systems.

The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.

RTMemController v1.0 Released

The Memory Team is proud to release another open-source tool to the community. This tool is called RTMemController and contains a mathematical formalization of the dynamic command scheduler introduced in Yonghui Li’s paper Dynamic Command Scheduling for Real-Time Memory Controllers that will be presented at ECRTS. The tool is capable of determining worst-case and average-case execution times of memory transactions of different transaction sizes and with varying degrees of bank interleaving.

An important driver for releasing this tool is to promote transparency and fair comparisons between work in the field. Longer term development plans for the tool may involve adding support for a memory controller front-end with different transaction schedulers, adding support for more memory generations (currently DDR3 is supported), and making the output compatible with DRAMPower to enable chaining the tools.

The official website of RTMemController is found here. Also check out the paper that describes the scheduling algorithm and its formalization.

Paper Accepted at ECRTS

Today, we congratulate Yonghui Li on an accepted paper at ECRTS. The paper is entitled Dynamic Command Scheduling for Real-Time Memory Controllers and presents both an architecture and analysis for a dynamically scheduled SDRAM controller supporting different transaction sizes and memory map configurations. This is Yonghui’s first accepted paper and we are proud to see that it got very good reviews from one of the most competitive conferences in the field. Now the work begins on preparing a camera-ready version and making the scheduling algorithm publicly available for comparisons in community.

Two Papers Accepted at DATE 2014

Today we celebrate that the Memory Team had both papers submitted to DATE accepted as full papers at the conference. The first paper was written by Manil Dev Gomony and is entitled “Coupling TDM NoC and DRAM Controller for Cost and Performance Optimization of Real-Time Systems”. This paper discusses area, power and performance benefits of coupling the arbitration in a TDM NoC with the memory controller arbitration, thereby reducing the number of arbitration points on the path from processor to memory. The second paper entitled “Exploiting Expendable Process-Margins in DRAMs for Run-Time Performance Optimization” was first-authored by Karthik Chandrasekar. This paper shows how to exploit excessive process margins in DRAMs by proposing a methodology for how to determine the minimum timings that a memory can safely run at, thereby improving performance.

Three Presentations at ESWEEK

The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!

DRAMPower v3.0 Released!

DRAMPower v3.0 has been released! The tool can now be employed with two interfaces: (1) Command traces and (2) Transaction traces (new feature). To facilitate usage of memory transaction traces, DRAMPower now includes an optional DRAM command scheduler, which dynamically schedules and logs DRAM commands, corresponding to the incoming memory transactions, as if it was connected to a memory controller. The scheduler assumes a closed-page policy, employs FCFS scheduling across transactions and uses ASAP scheduling for DRAM commands. This release also adds support for DDR4 and LPDDR3 devices and fixes minor bugs to improve the accuracy of DRAM power estimation. Click here to check it out.

Accepted Paper at CODES/ISSS 2013

Our paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” has been accepted at CODES/ISSS 2013. The paper is first-authored by Sven Goossens and builds on the work of Jasper Kuijsten, a graduated master student from the Memory Team. In this paper, we present a new architecture of our real-time memory controller that supports predictable and composable run-time reconfiguration on use-case transitions, which allows trade-offs between guaranteed bandwidth, response time and power. It also presents a methodology for offering composable service to memory clients by means of composable memory patterns, an extension to our existing pattern-based approach. Lastly, a reconfigurable Time-Division Multiplexing (TDM) arbiter and an associated reconfiguration protocol are proposed. The TDM slot allocations can be changed at run time, while the predictable and composable performance guarantees offered to active memory clients are unaffected by the reconfiguration. The SDRAM controller has been implemented as a TLM-level SystemC model, and in synthesizable VHDL for use on an FPGA platform.