The past two months have been very good to us with five journal articles being accepted in something resembling a ketchup-effect. The most recent addition is an article entitled “Certifying Execution Time in Multicores” that was accepted by the Elsevier journal Science of Computer Programming. In essence, this article is a summary of the PhD dissertation of Vitor Rodrigues, whom I collaborated with over the past years. My main contribution to this work is proposing the latency-rate model as an abstraction of the service provided by a shared resource, such as a memory. We incorporated this model into Vitors timing analysis tool based on abstract interpretation to enable scalable timing analysis of multi-core platforms with shared resources.
ACM TECS Accepts Another Journal Article
ACM Transaction of Embedded Computing Systems (TECS) recently informed us that our article “Maximizing the Number of Good Dies for Streaming Applications in NoC-based MPSoCs under Process Variation” has been accepted for publication. This work nicely summarizes the dissertation of Davit Mirzoyan from his four year PhD studies at Delft University of Technology under the supervision of Kees Goossens and myself.
The article addresses design of real-time systems for streaming applications constrained by a throughput requirement with reduced design margins, referred to as better than worst-case design. The first contribution is a complete modeling framework that captures a streaming application mapped to a NoC-based multiprocessor system with voltage-frequency islands under process-induced die-to-die and within-die frequency variations. The framework is used to analyze the impact of variations in the frequency of hardware components on application throughput at the system level. The second contribution is a methodology to use the proposed framework and estimate the impact of reducing circuit design margins on the number of good dies that satisfy the throughput requirement of a real-time streaming application. It is shown on both synthetic and real applications that the proposed design approach can increase the number of good dies by up to 9.6% and 18.8% for designs with and without fixed SRAM and IO blocks, respectively.
Article Accepted in Real-Time Systems Journal
A journal article entitled “A Framework for Memory Contention Analysis in Multi-Core Platforms” has been accepted for publication in Real-Time Systems. This article is a collaboration with Dakshina Dasari and Vincent Nelis and is a result from the time I spent with the CISTER-ISEP Research Unit in Porto.
The article proposes a unified framework to bound memory interference in multi-core platforms for a variety of different arbiters, such as time-division multiplexing (TDM), fixed priority, and an unspecified work-conserving arbiter. Our framework clearly demarcates the arbiter-dependent and independent stages in the analysis of interference. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to memory contention. We experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.
Two Articles Appeared in Journal of Systems Architecture
Two articles that were submitted to a Journal of Systems Architecture Special Issue on High-performance and Real-time Embedded Systems have now appeared online. The first article is called “T-CREST: Time-predictable Multi-Core Architecture for Embedded Systems” and summarizes the work done in the recently concluded FP7 STREP project T-CREST, where me and my students worked on time-predictable memory controllers.
The second article is entitled “Dataflow Formalisation of Real-Time Streaming Applications on a Composable and Predictable Multi-Processor SOC” and shows how data-flow graphs can be used to model streaming applications mapped to the CompSoc platform and predict its minimum throughput. The basic idea is to start from a data-flow graph of the application and add additional nodes and edges that capture the mapping and timing behavior of all hardware components software libraries, and schedulers in the system. The approach is verified by comparing the predicted performance to the actual performance of an application executing on a CompSoc instance on an FPGA. The article clearly demonstrates the potential of modeling systems in which the behavior of all hardware and software components are known.
Paper Accepted at RTAS 2015
We just had a paper accepted at the Real-Time and Embedded Technology and Applications Symposium (RTAS) in Seattle. The paper is entitled “An Efficient Configuration Methodology for Time-Division Multiplexed Single Resources” and presents an ILP-based methodology to allocate TDM slots to resource clients, such that bandwidth and latency constraints are satisfied while resource utilization is minimized. A heuristic algorithm is furthermore proposed to determine the number of TDM slots in the schedule. This paper is a collaboration both with colleagues here at CTU Prague and with Andrew Nelson from Eindhoven University of Technology.
For the camera-ready version of the paper, please click here.
Paper Accepted at PDP 2015
Today, we congratulate Hazem Ali for having a paper accepted at PDP 2015. The paper is entitled “Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs” and proposes a heuristic methodology for extracting real-time parameters, such as periods, deadlines and offsets, for applications specified as homogeneous synchronous data-flow (HSDF) graphs. The benefit of the approach is that it enables HSDF applications to be analyzed using traditional real-time techniques and scheduled with common real-time schedulers, such as earliest-deadline first.
Memory Team has Two Papers Accepted at DATE 2015
The notifications from the DATE conference are in and the Memory Team scores 2 out of 2, just like in 2014. The first paper entitled “A Generic, Scalable and Globally Arbitrated Memory Tree for Shared DRAM Access in Real-Time Systems” was first-authored by Manil and is a collaboration with Jamie Garside and Neil Audsley from University of York. The paper proposes a memory interconnect for shared memory architectures in many-core systems. A main architectural feature is that the interconnect is heavily pipelined enabling it to be synthesized at high frequencies even with a large number of clients. Another highlight is that it has global arbitration that can be programmed to behave like several different arbitration mechanisms, such as TDM, CCSP and FBSP.
The second paper “Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs”was first-authored by our colleagues at Kaiserslautern University of Technology in collaboration with Sven Goossens from our Memory Team. This paper looks into the thermal behavior of 3D-stacked WIDE I/O DRAM and compares its impact on retention time and bit error rates to conventional 2D DRAM chips.
Article in ACM Transactions on Embedded Computing Systems (TECS)
Manil Dev Gomony just had his first journal article accepted in ACM Transactions on Embedded Computing Systems. The article is entitled “A Real-Time Multi-Channel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels” and is an extension of his DATE paper from 2013, which was the first paper to provide architectures and techniques for multi-channel memory controllers in real-time systems.
The two main contributions of the article are: 1) A configurable real-time multi-channel memory controller architecture with a novel method for logical-to-physical address translation. 2) Two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. The mapping algorithms are experimentally evaluated, showing benefits over two state-of-the-art mapping algorithms. Finally, a case study is presented that demonstrates how to configure a Wide IO DRAM in a High-Definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of the work.
Article in Real-Time Systems Journal has Appeared
A journal article entitled “Unified overhead-aware schedulability analysis for slot-based task-splitting” has appeared in Real-Time Systems Journal. This article was first-authored by Paulo Baltarejo Sousa during my time at CISTER-ISEP Research Unit in Porto, Portugal and is the result of a collaboration from that time.
The main contribution of the article is a unified scheduling theory for two state-of-the-art slot-based semi-partitioned algorithms, S-EKG and NPS-F. This new theory is based on exact schedulability tests, thus also overcoming many sources of pessimism in existing analyses. Another benefit of the proposed analysis is that it captures overheads, such as interrupts, context switches, and caches, occurring when tasks are deployed on real multi-core platforms. Together, these advantages results in a new efficient and reliable schedulability analysis for slot-based task-splitting algorithms.
Paper Accepted at ECRTS
Today, we congratulate Yonghui Li on an accepted paper at ECRTS. The paper is entitled Dynamic Command Scheduling for Real-Time Memory Controllers and presents both an architecture and analysis for a dynamically scheduled SDRAM controller supporting different transaction sizes and memory map configurations. This is Yonghui’s first accepted paper and we are proud to see that it got very good reviews from one of the most competitive conferences in the field. Now the work begins on preparing a camera-ready version and making the scheduling algorithm publicly available for comparisons in community.