Another successful collaboration has resulted in an accepted publication at the Fifteenth International Symposium on Practical Aspects of Declarative Languages (PADL). The title of the paper is “A Declarative Compositional Timing Analysis for Multicores Using the Latency-Rate Abstraction” and it was written together with Vitor Rodrigues, Simão Melo de Sousa, and Mário Florido from Universidade do Porto and Universidade da Beira Interior. The paper discusses the theory and declarative implementation of timing analysis for multi-cores using abstract interpretation. To manage the state-space explosion of possible interleavings of requests from different cores to shared resources, the latency-rate abstraction is proposed and proven to be sound in the context of the proposed analysis. The resulting loss of precision is then evaluated for a simple system where a memory is shared using TDM arbitration.
Memory Team Scores Four out of Four Accepted Papers at DATE 2013!
The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:
- Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers
- Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis
- System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
- Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller
The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.
Paper Accepted at ESTIMedia 2012
Andrew Nelson just had a paper “Power Versus Quality Trade-offs for Adaptive Real-Time Applications” accepted at ESTIMedia 2012. The paper is based on the work of Sjoerd te Pas, one of my graduated master students, and discusses how power consumption can be traded for application quality for adaptive real-time applications using existing DVFS techniques. The techniques are demonstrated for an H.263 application on an FPGA instance of the CompSOC platform. Stay tuned for the camera-ready version.
Update: The paper is now available online. Click here to read it.
Visiting Researcher at CISTER
For the next six months, I am a visiting resarcher at CISTER (Research Centre in Real-Time Computing Systems) based at the School of Engineering (ISEP) of the Polytechnic Institute of Porto (IPP), Portugal. This gives me a great opportunity to work with some of the great minds in the real-time community, broaden my knowledge by exploring new applications and research areas, as well as contribute with my experiences to the group. At this point, I am familiarizing myself with the work carried out in the group and the work plan will be defined during the coming month.
Update: After settling in at CISTER, I am now working on two projects. The first one relates to their work on bus contention analysis, which is a familiar topic with a different twist. The second project is related to implementation and evaluation of scheduling algorithms in the Linux kernel, which is a completely new topic. Of course, I am also still spending time managing the work of the memory team in Eindhoven. Some new, some old, but in the end I am learning many new things both technically and culturally, and I am meeting many extraordinary people.
Tutorial Accepted at HiPEAC 2013
Our tutorial Designing Next-Generation Real-Time Streaming Systems was accepted at HiPEAC 2013, which takes place in Berlin January 2013. The tutorial is a collaboration between Eindhoven University of Technology, ST-Ericsson and Saarland University, and presents, among other things, predictability concepts from the CompSOC platform and its associated toolchain. We hope to see you there!
The tutorial webpage is available here.
5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems
I have been appointed program co-chair of the on 5th Workshop Compositional Theory and Technology for Real-Time Embedded Systems (CRTS 2012) together with Bjorn Andersson from the Software Engineering Institute at Carnegie Mellon University, USA. The workshop is co-located with the Real-Time Systems Symposium (RTSS) in Puerto Rico and takes place on December 4th, 2012. The goal of the workshop is to reduce the increasing design and analysis cost of real-time embedded systems by proposing solutions based on compositional platforms and methodologies. These enable decomposition of a complex systems into components that can be designed and analyzed in isolation and then integrated using interfaces with clearly defined temporal and functional properties. We gladly invite you to submit contributions to the workshop or to participate during your stay at RTSS.
Click here to visit the workshop website.
Karthik Chandrasekar Receives HiPEAC Collaboration Grant
Today, we celebrate that Karthik Chandrasekar has received a 3 month HiPEAC collaboration grant to visit the group of Prof. Norbert Wehn at Kaiserslautern Institute of Technology. The application process was competitive with approximately 30% of 67 proposals being funded. The grant serves to extend the existing collaboration between our two groups and will be used to conduct research on the hot topic of “Mobile and 3D-Stacked Wide I/O DRAM Power Modeling and Optimization”.
Paper Accepted at DSD 2012
The memory team congratulates Gervin Thomas from TU Berlin for having his paper entitled “A Predictor-based Power-Saving Policy for DRAM Memories” accepted at DSD 2012. This work is the result of Gervin’s HiPEAC collaboration visit in Eindhoven between August and October 2011. During this time, he worked closely with Karthik Chandrasekar on finding a way to use the self-refresh mode of DRAMs to reduce the power consumption in soft real-time systems without significantly reducing performance. The camera-ready version of the paper will be available shortly.
Update: The paper is now available online. Click here to read it.
New PhD Student on the Memory Team
The memory team welcomes Yonghui Li who just embarked on the four year quest towards a PhD degree in the context of the T-CREST project. We wish him the best of luck on this endeavor and look forward to working together.
CoMPSoC Website Launched – compsoc.eu
The CoMPSoC project has launched an official website, www.compsoc.eu, with information about the research, references to key publications, and links to the websites of the individual websites of the researchers. I recommend having a look at this website, since it shows the system-level context, the bigger picture, of the memory controller research done by the memory team.
Update: The DATE demo is now posted on compsoc.eu for those that were unable to see it in Dresden.
Click here to enjoy the demo.