Invited Presentation at CMAS 2015

I have recently accepted an invitation to speak at the First TCRTS Workshop on Certifiable Multicore Avionics Systems (CMAS), which takes place on April 13 and is co-located with RTAS 2015 in Seattle. The presentation is made in collaboration with Jan Nowotsch at Airbus Group Innovations, where I was a Visiting Researcher during two months last year. The title of the presentation is Towards Certifiable Resource Sharing in Safety-Critical Multi-Core Real-Time Systems and discusses current problems and state-of-the-art methods for resource sharing in real-time multi-core platforms. The abstract of the presentation is found below:

The proliferation of multi-core platforms has had great impact on embedded computing. Multiple cores exploiting task-level parallelism offer performance far beyond what is possible with a single core, while staying within an acceptable power envelope. Since resources, such as interconnect and memories, are often shared between cores, the platforms have also become increasingly cost efficient. However, resource sharing results in interference between concurrently executing applications, which causes problems in real-time systems where such interference must be either bounded or completely eliminated. As a result, safety-critical systems, for example in the avionics domain, have not yet been able to capitalize on the benefits of multi-core platforms due to stringent certification requirements.

This presentation discusses the state-of-the-art in resource sharing in multi-core systems and its application to safety-critical real-time systems. First, a survey of efforts to build time-predictable resources, such as interconnects and memory controllers, is provided. Then, software-based interference mitigation mechanisms and analyses for these resources in commercial-of-the-shelf platforms are discussed. This is followed by an overview of the approach proposed by Airbus Group Innovations to manage interference and compute worst-case execution times of applications running on a Freescale P4080 multi-core platform. The presentation is concluded by highlighting open issues and future directions towards certifiable resource sharing in safety-critical multi-core real-time systems.

Update: The slides are available here.

Three Presentations at ESWEEK

The Embedded Systems Week kicks off next week in Montreal, Canada. Two of my students will be giving a total of three presentations, which may be interesting for those following my work. First, Sven Goossens will be presenting his CODES+ISSS paper “A Reconfigurable Real-Time SDRAM Controller for Mixed Time-Criticality Systems” on Monday September 30 10:30 – 11:00. On Thursday October 3, approximately, 09:50 – 10:10, he will also summarize all of his work on memory controllers for mixed time-criticality systems in an invited presentation entitled “A Mixed Time-Criticality SDRAM Controller” at the Memory Architecture and Organization Workshop (MeAOW). At almost the same time, October 3 10:00 – 10:30, Davit Mirzoyan will present his paper “Throughput Analysis and Voltage-Frequency Island Partitioning for Streaming Applications under Process Variation” at the Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia). We hope to see you there!

Invited Presentations in Northern, Southern, and Central Europe

The next two weeks involves quite a marketing effort, as I will give three invited presentations about real-time memory controllers in northern, southern, and central Europe, respectively. Tomorrow, I will present our work at the Faculty of Information Technology at Czech Technical University in Prague. On Friday, I will meet with Karl-Erik Arzen and Enrico Bini at the Department of Control at Lund’s Institute of Technology and share my story. Lastly, next week Wednesday, I present at the ReTiS Lab at Scuola Superiore Sant’Anna. I thank all these institutes for the opportunity to present and I hope they will enjoy the story.