Paper Accepted at DAC 2013

For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.

Update: The paper is now available online. Click here to read it.

Back in Eindhoven

After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.