Vacancy for a PhD in Energy Labels for Digital Services

Back in July, I announced that our project proposal “Zero-Waste Computing: Energy Labels for Digital Services” was granted for the Science and Design PhD program at the University of Amsterdam. Now, the Parallel Computing Systems (PCS) group  is looking for a suitable PhD candidate for this project. Among other things, this involves modelling and monitoring to determine how energy is consumed in digital services whose computations are distributed over device, edge, and cloud.

Find a more detailed description of the vacancy, as well as instructions for how to apply here. The application period ends on October 18.

Article about Survey-based Study into Industry Practice in Real-time Systems in Real-time Systems Journal

It has been almost a year since we published the first survey-based study in the area of real-time systems at the Real-time Systems Symposium (RTSS) back in December 2020. The paper was entitled “An Empirical Survey-based Study into Industry Practice in Real-time Systems” and had the ambitious goal of addressing the gap between academic research and industry practice through an empirical survey-based study into industry practice. The survey had five objectives: 1) Establish whether timing predictability is of concern to the real-time embedded systems industry, 2) Identify relevant industrial problem contexts, including hardware platforms, middleware, and software, 3) Determine which methods and tools are used to achieve timing predictability, 4) Establish which techniques and tools are used to satisfy real-time requirements, and 5) Determine trends for future real-time systems. The survey was completed by 120 industry practitioners in the field of real-time embedded systems, which allowed interesting observations and insights to be made about the characteristics of the systems being developed today and important trends for the future.

Now, almost one year later, I am happy to announce that an extended version of our RTSS paper has been accepted for publication in the Real-time Systems journal. The title of the article is “A Comprehensive Survey of Industry Practice in Real-Time Systems“. The main extensions in the article include: 1) a discussion of potential threats to validity of the survey and its results, as well as the steps taken to mitigate them, 2) a statistical analysis and discussion of the results of the survey, in the context of its five objectives, 3) a discussion of the results of a quiz aimed at determining if the aggregate findings of the survey are common knowledge in the real-time systems community. In addition, more aggregated data from the survey has been released, allowing interested readers to further delve into the similarities and differences between the avionics, automotive, and consumer electronic domains.

We hope that you enjoy the article!

Paper about Model-driven System Performance Engineering Accepted at ESWEEK Industry Session

The System Performance Expertise Team at ESI (TNO) has worked for a long time to consolidate our many years of experience across projects and companies. This effort has now culminated in a paper entitled “Model-driven System Performance Engineering for Cyber-physical Systems“, which has been accepted for the industry session at the Embedded Systems Week (ESWEEK) in October.

The paper describes ESI’s current view on the field of System-Performance Engineering (SysPE). SysPE encompasses modeling formalisms, methods, techniques, and industrial practices to design systems for performance, where performance is taken integrally into account during the whole system life cycle. Industrial SysPE state of practice is generally model-based. Due to the rapidly increasing complexity of systems, there is a need to develop and establish model-driven methods and techniques. To structure the field of SysPE, the paper identifies: (1) industrial challenges motivating the importance of SysPE, (2) scientific challenges that need to be addressed to establish model-driven SysPE, (3) important focus areas for SysPE and (4) best practices. A survey was conducted to collect feedback on our views. The responses were used to update and validate the identified challenges, focus areas, and best practices. The final result is presented in this paper. Interesting observations are that industry sees a need for better design-space exploration support, more than for additional performance modeling and analysis techniques. Also tools and integral methods for SysPE need attention. From the identified focus areas, scheduling and supervisory control is seen as lacking established best practices.

The paper will be presented as a part of Industry Session 2 at ESWEEK on October 12. The second talk of that session presents why and how ITEC, Nexperia, a world-leading manufacturer of semiconductor equipment, is moving towards model-driven system-level development. The session ends with a moderated Q&A. Since ESWEEK is an online event this year, you can register for 20 USD if you want to attend the conference and the session.

Project Proposal about Energy Labels for Digital Services Granted

It is my pleasure to announce our project proposal entitled “Zero-Waste Computing: Energy Labels for Digital Services” has been granted for the Science and Design PhD program at the University of Amsterdam. Ana Lucia Varbanescu is the main applicant for this project, with Anuj Pathania and myself as co-applicants. The project proposal was supported by Surf, ESI (TNO), Barcelona Supercomputing Center, and ASTRON.

The project addresses the issue that digital services are getting increasingly prevalent in society and are vital to the Dutch economy, already reaching 60% of GDP. However, they come with a significant, rapidly-increasing energy cost, raising sustainability concerns, since a mid-size datacenter alone consumes as much energy as a small town. However, datacenters are only the final link in a digital chain. Users interacting with devices — mobile phones, tablets, or laptops — trigger entire digital chains, combining multiple communicating computing layers and data transfers: from the device itself, through the edge, to the datacenter. Each layer has its own computing infrastructure (see figure). At each layer, decisions are made about how, where and when applications are running and/or data are transferred. These decisions have a significant impact on the user-perceived quality-of-service (QoS), but also on the energy consumption – per layer, and for the entire digital chain. The energy footprint of different devices along the chain might be known, but the actual energy consumed by the application is unknown, because it depends on infrastructure choices, and on user QoS requirements, and on mapping decisions made on the edge and in the datacenter. Thus, the energy efficiency, i.e., the amount of energy consumed to perform the actual task at hand, is largely unknown, for most digital chains.

We argue that the first step to reduce waste in computing is to quantify the energy efficiency of end-to-end digital chains. Our project focuses on designing an integrated framework (i.e., the methods, metrics, and tools) for this quantification effort. Specifically, we aim to define a reference architecture of digital chains, use it to define an analytical digital-chain energy-efficiency model that exposes the factors that impact energy efficiency along the chain, and support it with a high-level functional simulator to assess different operational scenarios and parameters that affect the energy efficiency of digital chains.

This is a small project funding only a single PhD student. More momentum is required to further advance this area and make a step from only monitoring the energy consumption of digital chains to also include actuation, e.g. energy minimization through workload redistribution, subject to performance constraints. We are currently looking for interested parties to collaborate with us on this topic in future project proposals.

Modelling and Analysis of Component-based Systems (MOANA-CBS) Course Update

Last year, ESI (TNO) and Thales developed a two-day course on Modelling and Analysis of Component-based Systems (MOANA-CBS) as a part of the DYNAMICS project. The course addresses the trend to tackle software complexity by decomposing monolithic software into loosely coupled components. While this trend manages complexity through improved scalability, adaptability, and testability, it also increases concurrency and asynchronous communication. This may in turn lead to an explosion in possible behaviors. As a consequence, it is hard to oversee the behavior of such systems, resulting in situations where early design errors are detected much later in the system lifecycle with exponentially rising costs. The course targets software and system architects/engineers involved in design and implementation of components and interfaces, and teaches methods for modelling and analyzing them to guarantee that they are free from deadlocks, livelocks, races, and buffer overflows.

We piloted the course material both in academic and industrial environments. The former was as a part of my course Embedded Software and Systems, a part of the Software Engineering Master  at the University of Amsterdam. The latter was as a part of the Accelerate program run by Thales and Luminis to accelerate their medior software talent to a senior level. Thales recently published an interview with Patrick Schulenberg, one of the participants in the program, about his experience. Patrick explains that the program has been an excellent opportunity for him to grow within the company, and mentions the positive impact of our course: “ESI taught a class about interface modeling, sharing their experiences with using the Comma framework at Philips – this was a trigger for us to put practical modeling proficiency on our roadmap”.

Currently, we are developing an updated version of the MOANA-CBS course that will have closer ties to ComMA, an open-source domain-specific language initially developed by Philips and ESI that is currently used by several companies. This update will strengthen the practical applicability of the course for users of ComMA, and will introduce unfamiliar users to interface modelling and analysis through hands-on experience with the tool. The new version of the course is expected to be ready in Q3.

Paper Accepted at PNSE 2021

It has been almost a year since Mohammed (Madiou) Diallo submitted his bachelor thesis “Towards the Scalability of Detecting and Correcting Incompatible Service Interfaces“, which he carried out in the context of the DYNAMICS project, an applied research project between ESI (TNO) and Thales. After the thesis was finished, we discussed publishing the work as a paper and one year later, a slightly restructured and simplified version of the story has been accepted at the International Workshop on Petri Nets and Software Engineering (PNSE), a workshop co-located with the Petri Net conference.

The accepted paper is entitled “Synthetic Portnet Generation with Controllable Complexity for Testing and Benchmarking” and presents a heuristic-driven method for synthetic generation of random portnets, a kind of Petri Nets suitable for modelling software interfaces in component-based systems. The method considers three user-specified complexity parameters: the expected number input and output places, and the prevalence of non-determinism in the skeleton of the generated net. An implementation of this method is available as an open-source Python tool. Experiments demonstrate the relations between the three complexity parameters and investigate the boundaries of the proposed method. This work was helpful for the DYNAMICS project, as it allowed us to synthetically generate a large number of interfaces of varying complexity that we could use to evaluate the scalability of existing academic tools for adapter generation.

 

 

Open-source ComMA v0.1.0 officially released

Last week, the open sourcing of ComMA (Component Modelling and Analysis) in the context of the Eclipse Foundation, saw another milestone. The first version Eclipse CommaSuite is now online in the form of Release 0.1.0. ComMA is a set of DSLs used to (partially) specify the behavior of components and their interfaces, including time and data constraints. On the basis of these specifications, a number of artifacts can be automatically generated, including run-time monitors that validate compliance with the specification can be generated, visualizations, timing statistics, documentation, test cases, and adapters. Many of these features will be included in later releases of ComMA, and some of them have yet to emerge from research projects as mature features.

ComMA was originally developed by ESI and Philips, but more recently in collaboration with a growing number of other companies. For example, the DYNAMICS project in which ESI works together with Thales, we are currently investigating how adapters can be semi-automatically generated to bridge differences between components implementing different versions of interfaces. This work has been previously mentioned in an article in Bits & Chips, as well as in a paper. Currently, three master students from my Embedded Software and Systems course at UvA are also doing their graduation projects in the context of evolution of ComMA interfaces, looking into aspects of data dependencies, interface dependencies, and static impact analysis. We look forward to seeing the results of their work this summer.

You can read more about ComMA in this news article TNO published this week.
Update: The news article is now also published in Bits & Chips

ESI Featured in Nederland Maakt Het

ESI (TNO) was featured in the latest episode (Season 4 Episode 1) of Nederland Maakt Het, a program on RTL Z about Dutch organizations that develop of apply innovative technologies. In the segment, Wouter Leibbrandt, the Research and Operations director at ESI, explains that the Netherlands has a powerful high-tech industry, which is important to its competitiveness and earning power. To stay at the top and continue to develop excellent products in light of increasing system complexity, it is important to invest in research and development of new design methodologies. Big high-tech companies do this in an open innovation environment to address the challenges they face together. ESI is the applied research organization and knowledge partner that brings the industry and academic parties together into an eco-system to facilitate this.

In my role as part-time professor at UvA, I explain my view on open innovation and how universities contribute and get value from the eco-system. In the Embedded Software and Systems course at the University of Amsterdam, which is an academic partner of ESI since 2021, I discuss the increasing system complexity with my students and teach model-based engineering methodologies to help them address this challenge. I also supervise students that want to contribute to solving the complexity problem by doing their thesis project in with ESI or in industry.  Lastly, Hein Otto Folkerts, the (former) head of Research at ASML, provides the industry view and explains the value of open innovation to ASML, one of the big high-tech companies in the Eindhoven region.

For those of you that missed the episode, it is available for online viewing on RTL XL. The segment about ESI starts at 14m30s and last for about 4 minutes. ESI also has a version of this segment in its own house style that is used for promotional purposes. This version is available here:

Official Project Kick-off for DSE 2.0

Today was the official project kick-off for the research project “Design Space Exploration 2.0: Towards Optimal Design of Complex, Distributed Cyber Physical Systems”. This project is a part of the Partnership Program Mastering Complexity (MasCot), funded by NWO Domain Applied and Engineering Sciences (AES) together with ESI (TNO). The University of Amsterdam and Leiden University are the academic partners, spearheaded by Andy Pimentel and Todor Stefanov. The carrying industrial partner is ASML, but with Philips, Siemens and ESI as parts of the user committee.

The main goal of the project is to extend existing methods for design-space exploration, often developed for on-chip systems, to cover complex distributed cyber-physical systems (dCPS), such as the lithography machines made by ASML. Designers of such systems need quick answers to so-called “what-if” questions with respect to possible design decisions/choices and their consequences on non-functional properties, such as system performance and cost. This calls for efficient and scalable system level design space exploration (DSE) methods that integrate appropriate application workload and system architectures models, simulation and optimization techniques, as well as supporting tools to facilitate the exploration of a wide range of design decisions. However, such DSE technology for complex dCPS does currently not exist. This projects hence tries to answer the question of how perform efficient and effective DSE for complex, distributed cyber-physical systems.

In today’s kick-off meeting, all stakeholders in the project had an opportunity to introduce themselves and refamiliarize themselves with the project and its goals. The two PhD students who will be working on the project, Marius and Faezeh, from UvA and Leiden, respectively, also gave a brief overview of the work they had done in the first three months of the project, which included a literature review and generation of high-level simulation models for different parameter settings.

I am directly involved in this project through my part-time appointment at UvA. As Marius’ second promotor, I will help him on his journey towards a PhD. I also have an interest in this project as an ESI Research Fellow and part of the MasCot Core Team. In this capacity, I am happy to help linking this project to ESI’s applied research projects, in particular at ASML, to exploit possible synergies, and to stimulate exchanges with other projects in the MasCot program.

Thales and University of Amsterdam Strengthen the ESI Ecosystem

ESI has just made a press release to announce that both Thales and the University of Amsterdam (UvA) has joined as partners in its open-innovation ecosystem. ESI’s ecosystem, based on open innovation, plays an important role in maintaining the leading competitive position of the Dutch high-tech industry. Together with universities and partner companies, ESI develops methodologies and tooling that are in line with the vision and needs of the high-tech industry, making use of the latest insights from universities. In an industry-as-a-lab setting, system engineering methodologies are developed, tested and validated on site at and with partners.

With the addition of UvA and Thales, ESI’s ecosystem now has more industrial and academic partners than ever before, which shows great promise in difficult times. Personally, I am very happy to see that the university where I work decided to further invest in its collaboration with ESI and join the partner board. Similarly, Thales is the company I have worked with in applied research projects for the past five years, and it pleases me that they see the benefits of this collaboration.

Read the full press release from ESI here.

Update:
The press release was picked up by a number of different media outlets, e.g.

UvA – UvA Informatics Institute and Thales strengthen ESI open-innovation ecosystem

Bits & Chips – Thales and UvA (re)join ESI

Emerce – Thales en het Informatica Instituut van de Universiteit van Amsterdam versterken ESI (TNO) open-innovatie ecosysteem

Link Magazine -Thales en de Universiteit van Amsterdam versterken het open-innovatie systeem van ESI TNO 

Engineers Online – Thales en UvA versterken Esi open-innovatie ecosysteem voor hightech