The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:
- Conservative Open-page Policy for Mixed Time-Criticality Memory Controllers
- Bounding SDRAM Interference: Detailed Analysis vs. Latency-Rate Analysis
- System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs
- Architecture and Optimal Configuration of a Real-Time Multi-Channel Memory Controller
The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.