On Wednesday, William Ford, a master student from VU/UvA defended his master thesis “Network Delay Model Creation and Validation for Design Space Exploration of Distributed Cyber-Physical Systems“. This thesis was executed in the context of the MasCot project DSE2.0 and was supervised by Benny and Faezeh Sadat Saadatmand, PhD student at Leiden University.
William’s thesis focuses on improving the development process of complex distributed cyber-physical systems (dCPS), such as the equipment developed by high-tech companies like ASML, Canon Production Printing, and Philips. Building physical prototypes for these systems is complex and costly, so the thesis explores automated and scalable model-based Design Space Exploration (DSE) as a solution. The research addresses the challenge of modeling network delays in dCPS, aiming to create models that balance speed and accuracy for DSE purposes. The methodology includes formalizing network topology and traffic concepts, resulting in an open-source framework for synthetic network generation called GeNSim. Three analytical network delay models—Constant Delay, Constant Bandwidth, and Latency-Rate, and a simulation-based approach using the INET framework—are proposed and evaluated synthetic networks and an industry case study at ASML. The findings reveal that each model has its strengths and weaknesses, with no single model meeting all requirements perfectly. Therefore, a multi-step modeling approach is suggested to leverage the strengths and mitigate the weaknesses of the different models.
William confidently presented his thesis. In particular, the committee was very happy with the Q&A session after the presentation, which resulted in a lively back and forth with interesting questions and answers. Having defended his thesis, William can now apply for his diploma and graduate. We thank William for his contributions to the DSE2.0 research and wish him all the best with his future career.
