Benny Akesson

Senior Research Fellow @ TNO-ESI | Endowed Professor @ University of Amsterdam

MasCot Program: Bridging Academia and Industry for High-Tech Innovation in Bits & Chips Feature

An article about strategic academic programming at TNO-ESI has appeared in Bits & Chips. The MasCot program, a collaboration co-funded by ESI and the Dutch research council NWO, is designed to tackle the increasing complexity of high-tech equipment.  The program addresses the pressing need for advanced engineering methodologies through four projects covering essential topics, such as design space exploration during early system design, scheduling, verification, and restructuring of evolving software. In the article, I explain how the 3-million-euro program facilitates the transition of academic research into practical industrial applications, creating an innovation funnel that spans from academic research through applied research to industrial embedding. The program’s strategic approach not only mitigates the risks associated with high-reward, complex projects but also fosters a symbiotic relationship between academia, industry, and TNO, allowing for a continuous exchange of knowledge, challenges, and innovations.

Master Thesis Shines Light on Hardware Dimensioning for Cyber-Physical Systems

On Wednesday, Marijn Vollaard defended his master thesis “Hardware Dimensioning for Microservice-based Cyber-Physical Systems: A Profiling and Performance Prediction Method” at the University of Amsterdam. This research has been supervised by Ben Pronk and myself as a part of a project with TNO-ESI.

The thesis addresses the problem of determining the number of homogeneous compute nodes needed for a particular variant of a cyber-physical system to meet its timing requirements. This is important in early discussions with customers and bidding processes, since it affects the size and cost of the resulting system. To this end, the thesis proposes a structured hardware dimensioning methodology comprising a profiling method and a performance prediction method. The four novel contributions of the thesis are: 1) A component-based profiling method, 2) a performance prediction method, 3) a structured hardware dimensioning methodology, and 4) validation of the approach, using a case study that represents a prototype of a CPS. Experimental evaluations on the case study show that the predicted performance differs from measurements on the application by at most 20%, which is satisfactory for hardware dimensioning decisions for new product variants.

The defense went well and Marijn confidently presented his story and convincingly answered the questions of the audience. The examination committee, impressed by his work, awarded his thesis a well-deserved grade of 8. As we bid farewell to Marijn, embarking on his next career adventure, we also extend our heartfelt congratulations. He certainly has much to be proud of. We wish him all the best on his travels and in his future pursuits.

Mastering Complexity at ICT Open 2024

TNO-ESI is hosting a Mastering Complexity for Cyber-Physical Systems track at ICT Open 2024. The event will take place in Utrecht on April 10-11. My colleague Rosilde Corvino will be the track chair of this event, together with myself. Submit an abstract, poster, or demo now and share with the community how your work addresses the challenge of increasing complexity in cyber-physical systems. Contributions in areas including system architecting, system dependability, system evolvability, systems of systems, and system performance are welcome.

Call for abstracts, posters, and demos:
https://ictopen.nl/track-mastering-complexity-for-cyber-physical-systems-cpshttps://lnkd.in/enBaRjNZ

Submission link:
https://www.ictopen2024.nl/submit-an-abstract/https://lnkd.in/etghmm8F

Master’s Student Marijn Vollaard Shines with Study on Hardware Dimensioning for Microservice Applications in Cyber-Physical Systems

Our master’s student, Marijn Vollaard, has achieved a significant milestone by completing and presenting his literature study titled “Hardware Dimensioning for Microservice Applications in Cyber-Physical Systems: Current Directions and Challenges” The study addresses the challenge of dimensioning the number of compute nodes required to meet the performance demands of microservice-based applications in cyber-physical systems. It thoroughly reviews an extensive body of literature on application and system profiling, performance prediction, and design-space exploration to establish the current state of knowledge in this field. The survey culminates in a discussion about how the surveyed literature applies to microservice applications, the cyber-physical systems context, and the problem of hardware dimensioning. Overall, this is a nice piece of work with a lot of references presented in a systematic way. Congratulations to Marijn for his great effort!”

Master Thesis Tackles Architectural Anti-patterns in Microservice Applications

Today, we are delighted to announce the successful defense of the outstanding master’s thesis titled “Architectural Anti-Pattern Identification and Mitigation in Microservice Applications Based on Telemetry” by our master student, Amund Lunke Rohne from the University of Amsterdam. This master’s project was a collaborative effort involving TNO-ESI and Thales.

The thesis addresses the problem that microservices offer benefits like scalability and separation of concerns, but also introduce many complex service dependencies. The decomposition of microservice applications can impact system performance and maintainability and can lead to architectural anti-patterns over time. While simple anti-patterns can be detected using analysis of service dependencies, there is a lack of formal mathematical definitions which prevents more complex anti-patterns from being automatically detected by tools. The thesis introduces a novel model called Granular Hardware Utilization-Based Service Dependency Graph (GHUBS), a fine-grained model that captures the interactions dependencies between services at the level of individual requests. The GHUBS model can be manually specified in early design phases to validate a microservice decomposition, or automatically created using telemetry data from a running application. Mathematical formalizations are introduced for four common architectural anti-patterns and methods for automatically detecting them using the GHUBS model is presented. A method for recommending how to mitigate the identified anti-patterns based on the service dependencies in the GHUBS model, as well as resource utilization metrics for the services, is also presented. The approach is implemented in a tool called Televisor and validated through case studies on open-source microservice benchmarking applications, revealing instances of these anti-patterns.

We thank Amund for his work and a fruitful collaboration, and wish him the best of luck in his future career.

3rd Annual MasCot Program Day 2023 Focuses on Technology Transfer and Industry-Academia Collaboration

In a bid to spearhead advancements in engineering methodologies and manage the increasing complexity of industrial systems, the third annual Mastering Complexity (MasCot) Program Day was successfully held on Tuesday, October 10, 2023. The MasCot program, a six-year strategic academic initiative jointly funded by TNO-ESI and NWO, has brought together leading universities and research organizations to pioneer the next generation of engineering methods, promoting cost-effective and high-quality development of industrial systems. The program consists of four key projects: 1) Scheduling Adaptive Modular Flexible Manufacturing Systems (TU/e, TU Delft, Radboud University), 2) Programming and Validating Software Restructurings (TU Delft, TU/e), 3) Testing in Times of Continuous Change (Radboud University, Twente University), and 4) Design Space Exploration 2.0: Towards Optimal Design of Complex, Distributed Cyber Physical Systems (UvA, Leiden University).

This year, Radboud University hosted the event at Hotel Van der Valk Nijmegen-Lent, drawing a crowd of 38 attendees from academia, industry, NWO, and TNO-ESI. With the first MasCot projects set to conclude in 2024, the theme of this year's gathering revolved around technology transfer. The event commenced with project updates from each of the four projects. During breaks, attendees had the opportunity to engage in technical dialogues with PhD students, who presented their work on posters. A highlight of the day was the keynote address delivered by Sjoerd Verduyn Lunel, head of ASML research (a.i.). Verduyn. A key message of his presentation was the required improvement of productivity of design engineers by a factor of 2.5 in the next ten years to keep up the pace of innovation. ASML is therefore engaging in defining road maps and establishing long-term collaborations with academic partners and research organization, such as TNO. He also described how ASML are differentiating projects at different levels of maturity, from fundamental research to proofs-of-concept, and how they scale up and transfer knowledge between these phases. This keynote was well-appreciated and many participants were inspired by this structured approach to programming and managing research and innovation.

The afternoon was dedicated to breakout sessions where participants shared their perspectives on technology transfer and discussed the roles that various MasCot stakeholders—universities, industry, NWO, and ESI—can concretely play in facilitating this critical process. The day concluded with a networking session and dinner, marking another successful edition of the MasCot Program Day.

Prestigious Test Of Time Award at ESWEEK 2023 for Memory Controller Research

I am happy to announce that we received the Test Of Time Award for CODES+ISSS at ACM/IEEE Embedded Systems Week (ESWEEK) 2023 in Hamburg, Germany. The Test of Time Award is the most prestigious award of ESWEEK and honors the authors of papers of previous editions of the co-located conferences (CASES 2008, CODES+ISSS 2007, and EMSOFT 2007) that had the highest impact. We received this award for my first paper as a PhD student “Predator: a predictable SDRAM memory controller“, which written with co-authors Kees Goossens and Markus Ringhofer and published in CODES+ISSS 2007.

The paper addressed the problem of providing guarantees on bandwidth and latency to ports on an SDRAM memory controller, a key component of a system-on-chip. Previously, this was only done for statically scheduled memory controllers that assumed the workload of memory requests was known a priori. While this limitation was acceptable for simple systems, increasing integration of functionality in consumer electronics products like set-top boxes challenged this assumption, requiring more dynamic solutions. To this end, the paper presented concepts, hardware architecture, and performance analysis for a more dynamic SDRAM memory controller for real-time systems.

This work formed the base for my memory research, which evolved into a research line that would continue for over a decade and in which six PhD students eventually graduated. In total, this research resulted in a body of work of 30+ papers and two books, which together have been cited more than 2000 times. It also resulted in the open-source tool DRAMPower, which is used to estimate energy consumption of memories. This tool has been integrated in the popular Gem5 simulator and is widely used by the computer architecture community.

The paper was impactful because it was one of the first papers about memory controllers for real-time systems. More papers would follow from Barcelona Supercomputing Center, UC Berkley, and University of Waterloo. Step by step, the proposed memory controllers would become more dynamic and the analysis more sophisticated. This continued until the middle of the previous decade, at which the field moved more from proposing and analyzing new memory controller architectures for systems-on-chips to configuring and analyzing commercial-of-the-shelf memory controllers. This is still an active field of research in the real-time systems community today.

“Receiving this award is an unexpected honor, and I extend my heartfelt thanks to my co-authors and everyone that contributed to subsequent advancements in this field, in particular my former PhD students Karthik Chandrasekar, Manil Dev Gomony, Sven Goossens, Yonghui Li, and Anna Minaeva. Together, we created, developed, and matured the research field of memory controllers for real-time systems.”

Call for Papers and Experts – 30th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2024) in Hong Kong

I have the honor of being the Program Chair of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2024), located in Hong Kong May 13-16 next year. Please see the Call for Papers below.

Soon, it will be time to put together the Technical Program Committee (TPC) that will review and select the papers that will appear in the conference program. If you are interested in joining the TPC of this conference, or any other conference (co-)sponsored by the Technical Community of Real-Time Systems (TCRTS), please fill out the TPC self-nomination form as soon as possible. We always welcome self-nominations from our own community, but this year we especially encourage self-nominations from the academic performance engineering community, as well as members of the industry that work with real-time requirements or performance engineering, defined in a broad sense.

If you have any questions, please feel to reach out to me. If want to self-nominate, click this link. A self-nomination is not a firm commitment, it is just a declaration of interest that may result in an invitation.

———————————————————————————————————————

30th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2024)

Hong Kong, May 13-16, 2024

———————————————————————————————————————

CALL FOR PAPERS

———————————————————————————————————————

RTAS is a top-tier conference with a focus on time-sensitive systems. RTAS’24 invites papers describing case studies, applications, methodologies, and algorithms that contribute to the state of practice in design, implementation, verification, validation, and evolution of time-sensitive systems. RTAS’24 consists of two tracks:

  • Track 1. Systems and Applications;
  • Track 2. Applied Methodologies and Foundations.

In both tracks, papers must consider some kind of timing requirements. The timing requirements of interest are broadly defined and include not only classical hard real-time constraints, but also soft real-time, probabilistic, quality-of-service (QoS), throughput or latency requirements. The application area can be any type of time-sensitive systems, ranging from resource-constrained embedded systems to cyber-physical systems (CPS), cloud/edge/fog computing systems, cloud data centers, Internet of Things (IoT), mobile computing, robotics,  smart grid, and smart cities, as well as middleware and frameworks, machine learning in or for time-sensitive systems and signal processing algorithms that execute in real time. RTAS welcomes both papers backed by formal proofs, as well as papers that focus exclusively on empirical validation of timing requirements, e.g., using traces or performance models inferred from operational data. Research results from fundamental research, (case-driven) applied research, and (pragmatic) industry practice are all in scope.

RTAS’24 follows a double-anonymous peer reviewing process: author identities and affiliations will not be revealed to reviewers. Authors will have the opportunity to provide a response to reviews before acceptance decisions are made, solely to provide clarifications and correct misconceptions. The response will not allow authors to introduce new material beyond the original submission, or promise such material for the camera-ready version. There will be an optional evaluation process for accepted papers that assesses the reproducibility of the work.

Track 1: Systems and Applications

This track focuses on research of an empirical nature pertaining to (system- or component-) level analysis, optimization, and verification, as well as applications, runtime software, and hardware architectures for time-sensitive systems.

Topics relevant to this track include, but are not limited to:

  • time-sensitive applications
  • real-time and embedded operating systems,
  • hypervisors and runtime frameworks,
  • hardware architectures, memory hierarchies, FPGAs, GPUs and accelerators,
  • time-sensitive networks, CPS/IoT infrastructure,
  • microservice technologies, cloud and edge computing, real-time artificial intelligence and machine learning,
  • application profiling, WCET analysis, compilers, tools, benchmarks and case studies.

Papers discussing design and implementation experiences on real industrial systems are especially encouraged. Papers submitted to this track should focus on specific systems and implementations. Authors must include a section with experimental results performed on a real implementation, or demonstrate applicability to an industrial case study or working system. The experiment or case study discussions must highlight the key lessons learned. Simulation-based results are acceptable for architectural simulation, or other cases where authors clearly motivate why it is not feasible to develop and evaluate a real system.

Empirical survey-based research focused on the real-time systems field is also welcome in this track. This type of research uses surveys, questionnaires, interviews, use cases or other empirical techniques to obtain information about the past / current / future state of play in the research, design, development, verification, validation, and deployment of time-sensitive systems.

Track 2: Applied Methodologies and Foundations

This track focuses on fundamental models, and analysis techniques/methods that are applicable to time-sensitive systems to solve specific problems. The track welcomes knowledge-based models, models built from operational data, as well as a combination, and different types of analysis methods, including analytical, statistical, or probabilistic methods. Topics relevant to this track include, but are not limited to:

  • modelling languages, modelling methods, model learning, model validation and calibration,
  • scheduling and resource allocation,
  • system-level optimization and co-design techniques,
  • design space exploration,
  • verification and validation methodologies.

Papers must describe the main context or use case for the proposed methods giving clear motivating examples based on real systems. The system models and any assumptions used in the derivation of the methods must be applicable to real systems, and reflect actual needs. Papers must include a section on experimental results, preferably including a case study based on information from a real system. The use of synthetic workloads and models is acceptable if appropriately motivated and used to provide a systematic evaluation.

Important Dates

Submission Deadline (firm): October 31, 2023
Author Response Period: January 8-12, 2024
Author Notification: January 19, 2024
Conference Date: May 13-16, 2024

 

Bridging the Gap: Rethinking Real-Time Systems for Industry Success and Model-Driven Performance Engineering

The real-time systems community is shrinking and needs to bridge the gap between academic research an industry practice. In my pitch at ECRTS, I shared our view on model-driven system performance engineering for cyber-physical systems and encouraged the community increase its scope and take a broader responsibility for timing-related issues in systems to achieve those goals. This means working in more of the focus areas that we have identified in our vision and validated with our industry partners, but also reconsidering some directions in areas where work is already taking place. This means less focus on hard real-time requirements and formal methods and more focus on:

• system-level KPIs instead of meeting deadlines in subsystems
• soft real-time requirements
• timing requirements beyond software
• system performance modelling, model calibration, and model learning
• data-driven performance analysis, optimization, verification, and diagnostics, e.g. using traces

I encouraged the community to have a look at our vision for model-based system performance engineering for industrial cyber-physical systems and asked to think about how they could contribute through their current and future work.

Please have a look at our vision here.

Thanks to Bram van der Sanden, Kuan-Hsun Chen, Mitra Nasri, Geoffrey Nelissen, and Twan Basten for their help preparing the pitch.

Scaling the Future: Master Thesis Defense on Scalability in Simulation Environments for Distributed Cyber-Physical Systems

Today, we celebrate that Herman Kelder successfully defended his master thesis “Scalability in System-Level Simulation Environments for Distributed Cyber-Physical Systems“. This work was carried out in the context of the DSE2.0 project, where we address the complex scientific challenges involved in performing design-space exploration (DSE) for complex distributed cyber-physical systems (dCPS), such as lithography machines. Three key challenges in this context are: 1) automatically modelling the application and platform based on data from the running system, 2) scalable search and pruning algorithms that help navigate large design spaces efficiently, and 3) scalable simulation environments that allow many design points to be efficiently evaluated concurrently.

Herman’s thesis addresses the last of these three challenges. To facilitate scalable and efficient DSE for dCPS, an evaluation environment is proposed, implemented, and evaluated. The research considers key design considerations for developing a distributed evaluation workflow that can dynamically be adapted to enable efficient and scalable exploration of the vast design space of complex, distributed cyber-physical systems. Evaluation of the proposed environment employs a set of system models, representing design points within a DSE process, to assess the solution and its behavior, performance, capability, and applicability in addressing the scalability challenge in the context of DSE for dCPS. During the evaluation, the performance and behavior are investigated in three areas: (i) Simulation Campaign, (ii) Task Management Configuration, and (iii) Parallel Discrete-Event Simulation (PDES). Throughout the evaluation, it is demonstrated that the proposed environment is capable of providing scalable and efficient evaluation of design points in the context of DSE for dCPS. Furthermore, the proposed solution enables designers and researchers to tailor it to their environment through dynamic complex workflows and interactions, workload-level and task-level parallelism, and simulator and compute environment agnosticism.

Herman executed his project meticulously and delivered excellent research results, both in terms of concepts and implementation. Thank you very much for your contributions Herman and we hope to work with you again at some point.