Article Accepted in Real-Time Systems Journal

A journal article entitled “A Framework for Memory Contention Analysis in Multi-Core Platforms” has been accepted for publication in Real-Time Systems. This article is a collaboration with Dakshina Dasari and Vincent Nelis and is a result from the time I spent with the CISTER-ISEP Research Unit in Porto.

The article proposes a unified framework to bound memory interference in multi-core platforms for a variety of different arbiters, such as time-division multiplexing (TDM), fixed priority, and an unspecified work-conserving arbiter. Our framework clearly demarcates the arbiter-dependent and independent stages in the analysis of interference. The arbiter-dependent phase takes the arbiter and the task memory-traffic pattern as inputs and produces a model of the availability of the bus to a given task. Then, based on the availability of the bus, the arbiter-independent phase determines the worst-case request-release scenario that maximizes the interference experienced by the tasks due to memory contention. We experimentally evaluate the quality of the analysis by comparison with a state-of-the-art TDM analysis approach and consistently showing a considerable reduction in maximum interference.

Paper Accepted at PDP 2015

Today, we congratulate Hazem Ali for having a paper accepted at PDP 2015. The paper is entitled “Generalized Extraction of Real-Time Parameters for Homogeneous Synchronous Dataflow Graphs” and proposes a heuristic methodology for extracting real-time parameters, such as periods, deadlines and offsets, for applications specified as homogeneous synchronous data-flow (HSDF) graphs. The benefit of the approach is that it enables HSDF applications to be analyzed using traditional real-time techniques and scheduled with common real-time schedulers, such as earliest-deadline first.

Article in Real-Time Systems Journal has Appeared

A journal article entitled “Unified overhead-aware schedulability analysis for slot-based task-splitting” has appeared in Real-Time Systems Journal. This article was first-authored by Paulo Baltarejo Sousa during my time at CISTER-ISEP Research Unit in Porto, Portugal and is the result of a collaboration from that time.

The main contribution of the article is a unified scheduling theory for two state-of-the-art slot-based semi-partitioned algorithms, S-EKG and NPS-F. This new theory is based on exact schedulability tests, thus also overcoming many sources of pessimism in existing analyses. Another benefit of the proposed analysis is that it captures overheads, such as interrupts, context switches, and caches, occurring when tasks are deployed on real multi-core platforms. Together, these advantages results in a new efficient and reliable schedulability analysis for slot-based task-splitting algorithms.

Paper Accepted at RTCSA 2013

Today, we congratulate Hazem Ali for having his first paper accepted at RTCSA. The paper is entitled “Critical-Path-First Based Allocation of Real-Time Streaming Applications on 2D Mesh-Type Multi-Cores” and proposes a mapping strategy for streaming applications, represented as acyclic data-flow graphs with throughput requirements, to multi-core architectures under partitioned EDF scheduling. The key idea is to first map tasks on the critical-paths of the application to minimize their execution time and thereby increasing the chance to satisfy the throughput constraint. The camera-ready version is available here.

Hazem Ali is a PhD student at the CISTER-ISEP Research Unit in Porto, supervised by Luis Miguel Pinho and myself, and this paper is a result of my six month visit there last year and the fruitful collaboration it has resulted in afterwards.

Paper Accepted at SIES 2013

A paper entitled “Identifying the Sources of Unpredictability in COTS-based Multicore Systems” was accepted at SIES 2013. This paper was written together with Dakshina Dasari, Vincent Nelis, Muhammad Ali Awan and Stefan Petters and is the first accepted paper resulting from the six months I spent at the CISTER-ISEP Research Center in Porto. The contribution of the paper is a survey of sources of unpredictability in commercial-of-the-shelf multi-core systems and the state-of-the-art research that is addressing them.

Update: The paper is now available online here.

Back in Eindhoven

After six great months at the CISTER Research Unit in Porto, I am back at Eindhoven University of Technology. I really enjoyed the opportunity to work in another group and learn more about traditional real-time systems and their applications. It has been great to get to know new people in the real-time community, both professionally and as friends. A few papers have already been submitted as a result of this collaboration and there are more to come over the next few months. To all my friends and colleagues in Porto, thank you very much and I look forward to stay in touch with you.

Memory Team Scores Four out of Four Accepted Papers at DATE 2013!

The preliminary author notification for DATE 2013 is now available on the conference website and it reveals that the memory team scores an incredible four accepted papers out of the four submitted, resulting in an acceptance ratio of 100% for the team! The four paper titles are:

The papers cover topics ranging from memory controller architectures, configuration, and power modeling for Wide I/O memories to open-page policies in real-time memory controllers and a comparison between the tightness of bounds for the latency-rate abstraction and cycle-accurate simulation. These papers are also evidence of the many recent successful collaborations as there are authors from CISTER-ISEP Research Unit, Fortiss, and the Technical Universities in Eindhoven, Kaiserslautern and Munich.

Visiting Researcher at CISTER

For the next six months, I am a visiting resarcher at CISTER (Research Centre in Real-Time Computing Systems) based at the School of Engineering (ISEP) of the Polytechnic Institute of Porto (IPP), Portugal. This gives me a great opportunity to work with some of the great minds in the real-time community, broaden my knowledge by exploring new applications and research areas, as well as contribute with my experiences to the group. At this point, I am familiarizing myself with the work carried out in the group and the work plan will be defined during the coming month.

Update: After settling in at CISTER, I am now working on two projects. The first one relates to their work on bus contention analysis, which is a familiar topic with a different twist. The second project is related to implementation and evaluation of scheduling algorithms in the Linux kernel, which is a completely new topic. Of course, I am also still spending time managing the work of the memory team in Eindhoven. Some new, some old, but in the end I am learning many new things both technically and culturally, and I am meeting many extraordinary people.