For the second year in a row, Karthik Chandrasekar lands a paper at the prestigious Design Automation Conference (DAC). The paper is entitled “Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach” and discusses how to obtain more realistic power estimates with high-level power models by making them aware of process variation. Just like his recently accepted DATE paper, this work is a result of a successful collaboration with Christian Weis and Norbert Wehn at the University of Kaiserslautern.
Update: The paper is now available online. Click here to read it.